📄 cirrus_vga.c
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reg_value);#endif break; } return CIRRUS_HOOK_HANDLED;}/*************************************** * * I/O access at 0x3c6 * ***************************************/static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value){ *reg_value = 0xff; if (++s->cirrus_hidden_dac_lockindex == 5) { *reg_value = s->cirrus_hidden_dac_data; s->cirrus_hidden_dac_lockindex = 0; }}static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value){ if (s->cirrus_hidden_dac_lockindex == 4) { s->cirrus_hidden_dac_data = reg_value;#if defined(DEBUG_CIRRUS) printf("cirrus: outport hidden DAC, value %02x\n", reg_value);#endif } s->cirrus_hidden_dac_lockindex = 0;}/*************************************** * * I/O access at 0x3c9 * ***************************************/static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value){ if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) return CIRRUS_HOOK_NOT_HANDLED; *reg_value = s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 + s->dac_sub_index]; if (++s->dac_sub_index == 3) { s->dac_sub_index = 0; s->dac_read_index++; } return CIRRUS_HOOK_HANDLED;}static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value){ if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) return CIRRUS_HOOK_NOT_HANDLED; s->dac_cache[s->dac_sub_index] = reg_value; if (++s->dac_sub_index == 3) { memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3], s->dac_cache, 3); /* XXX update cursor */ s->dac_sub_index = 0; s->dac_write_index++; } return CIRRUS_HOOK_HANDLED;}/*************************************** * * I/O access between 0x3ce-0x3cf * ***************************************/static intcirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value){ switch (reg_index) { case 0x00: // Standard VGA, BGCOLOR 0x000000ff *reg_value = s->cirrus_shadow_gr0; return CIRRUS_HOOK_HANDLED; case 0x01: // Standard VGA, FGCOLOR 0x000000ff *reg_value = s->cirrus_shadow_gr1; return CIRRUS_HOOK_HANDLED; case 0x02: // Standard VGA case 0x03: // Standard VGA case 0x04: // Standard VGA case 0x06: // Standard VGA case 0x07: // Standard VGA case 0x08: // Standard VGA return CIRRUS_HOOK_NOT_HANDLED; case 0x05: // Standard VGA, Cirrus extended mode default: break; } if (reg_index < 0x3a) { *reg_value = s->gr[reg_index]; } else {#ifdef DEBUG_CIRRUS printf("cirrus: inport gr_index %02x\n", reg_index);#endif *reg_value = 0xff; } return CIRRUS_HOOK_HANDLED;}static intcirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value){#if defined(DEBUG_BITBLT) && 0 printf("gr%02x: %02x\n", reg_index, reg_value);#endif switch (reg_index) { case 0x00: // Standard VGA, BGCOLOR 0x000000ff s->cirrus_shadow_gr0 = reg_value; return CIRRUS_HOOK_NOT_HANDLED; case 0x01: // Standard VGA, FGCOLOR 0x000000ff s->cirrus_shadow_gr1 = reg_value; return CIRRUS_HOOK_NOT_HANDLED; case 0x02: // Standard VGA case 0x03: // Standard VGA case 0x04: // Standard VGA case 0x06: // Standard VGA case 0x07: // Standard VGA case 0x08: // Standard VGA return CIRRUS_HOOK_NOT_HANDLED; case 0x05: // Standard VGA, Cirrus extended mode s->gr[reg_index] = reg_value & 0x7f; cirrus_update_memory_access(s); break; case 0x09: // bank offset #0 case 0x0A: // bank offset #1 s->gr[reg_index] = reg_value; cirrus_update_bank_ptr(s, 0); cirrus_update_bank_ptr(s, 1); break; case 0x0B: s->gr[reg_index] = reg_value; cirrus_update_bank_ptr(s, 0); cirrus_update_bank_ptr(s, 1); cirrus_update_memory_access(s); break; case 0x10: // BGCOLOR 0x0000ff00 case 0x11: // FGCOLOR 0x0000ff00 case 0x12: // BGCOLOR 0x00ff0000 case 0x13: // FGCOLOR 0x00ff0000 case 0x14: // BGCOLOR 0xff000000 case 0x15: // FGCOLOR 0xff000000 case 0x20: // BLT WIDTH 0x0000ff case 0x22: // BLT HEIGHT 0x0000ff case 0x24: // BLT DEST PITCH 0x0000ff case 0x26: // BLT SRC PITCH 0x0000ff case 0x28: // BLT DEST ADDR 0x0000ff case 0x29: // BLT DEST ADDR 0x00ff00 case 0x2c: // BLT SRC ADDR 0x0000ff case 0x2d: // BLT SRC ADDR 0x00ff00 case 0x2f: // BLT WRITEMASK case 0x30: // BLT MODE case 0x32: // RASTER OP case 0x33: // BLT MODEEXT case 0x34: // BLT TRANSPARENT COLOR 0x00ff case 0x35: // BLT TRANSPARENT COLOR 0xff00 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 s->gr[reg_index] = reg_value; break; case 0x21: // BLT WIDTH 0x001f00 case 0x23: // BLT HEIGHT 0x001f00 case 0x25: // BLT DEST PITCH 0x001f00 case 0x27: // BLT SRC PITCH 0x001f00 s->gr[reg_index] = reg_value & 0x1f; break; case 0x2a: // BLT DEST ADDR 0x3f0000 s->gr[reg_index] = reg_value & 0x3f; /* if auto start mode, starts bit blt now */ if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) { cirrus_bitblt_start(s); } break; case 0x2e: // BLT SRC ADDR 0x3f0000 s->gr[reg_index] = reg_value & 0x3f; break; case 0x31: // BLT STATUS/START cirrus_write_bitblt(s, reg_value); break; default:#ifdef DEBUG_CIRRUS printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index, reg_value);#endif break; } return CIRRUS_HOOK_HANDLED;}/*************************************** * * I/O access between 0x3d4-0x3d5 * ***************************************/static intcirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value){ switch (reg_index) { case 0x00: // Standard VGA case 0x01: // Standard VGA case 0x02: // Standard VGA case 0x03: // Standard VGA case 0x04: // Standard VGA case 0x05: // Standard VGA case 0x06: // Standard VGA case 0x07: // Standard VGA case 0x08: // Standard VGA case 0x09: // Standard VGA case 0x0a: // Standard VGA case 0x0b: // Standard VGA case 0x0c: // Standard VGA case 0x0d: // Standard VGA case 0x0e: // Standard VGA case 0x0f: // Standard VGA case 0x10: // Standard VGA case 0x11: // Standard VGA case 0x12: // Standard VGA case 0x13: // Standard VGA case 0x14: // Standard VGA case 0x15: // Standard VGA case 0x16: // Standard VGA case 0x17: // Standard VGA case 0x18: // Standard VGA return CIRRUS_HOOK_NOT_HANDLED; case 0x19: // Interlace End case 0x1a: // Miscellaneous Control case 0x1b: // Extended Display Control case 0x1c: // Sync Adjust and Genlock case 0x1d: // Overlay Extended Control case 0x22: // Graphics Data Latches Readback (R) case 0x24: // Attribute Controller Toggle Readback (R) case 0x25: // Part Status case 0x27: // Part ID (R) *reg_value = s->cr[reg_index]; break; case 0x26: // Attribute Controller Index Readback (R) *reg_value = s->ar_index & 0x3f; break; default:#ifdef DEBUG_CIRRUS printf("cirrus: inport cr_index %02x\n", reg_index); *reg_value = 0xff;#endif break; } return CIRRUS_HOOK_HANDLED;}static intcirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value){ switch (reg_index) { case 0x00: // Standard VGA case 0x01: // Standard VGA case 0x02: // Standard VGA case 0x03: // Standard VGA case 0x04: // Standard VGA case 0x05: // Standard VGA case 0x06: // Standard VGA case 0x07: // Standard VGA case 0x08: // Standard VGA case 0x09: // Standard VGA case 0x0a: // Standard VGA case 0x0b: // Standard VGA case 0x0c: // Standard VGA case 0x0d: // Standard VGA case 0x0e: // Standard VGA case 0x0f: // Standard VGA case 0x10: // Standard VGA case 0x11: // Standard VGA case 0x12: // Standard VGA case 0x13: // Standard VGA case 0x14: // Standard VGA case 0x15: // Standard VGA case 0x16: // Standard VGA case 0x17: // Standard VGA case 0x18: // Standard VGA return CIRRUS_HOOK_NOT_HANDLED; case 0x19: // Interlace End case 0x1a: // Miscellaneous Control case 0x1b: // Extended Display Control case 0x1c: // Sync Adjust and Genlock case 0x1d: // Overlay Extended Control s->cr[reg_index] = reg_value;#ifdef DEBUG_CIRRUS printf("cirrus: handled outport cr_index %02x, cr_value %02x\n", reg_index, reg_value);#endif break; case 0x22: // Graphics Data Latches Readback (R) case 0x24: // Attribute Controller Toggle Readback (R) case 0x26: // Attribute Controller Index Readback (R) case 0x27: // Part ID (R) break; case 0x25: // Part Status default:#ifdef DEBUG_CIRRUS printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index, reg_value);#endif break; } return CIRRUS_HOOK_HANDLED;}/*************************************** * * memory-mapped I/O (bitblt) * ***************************************/static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address){ int value = 0xff; switch (address) { case (CIRRUS_MMIO_BLTBGCOLOR + 0): cirrus_hook_read_gr(s, 0x00, &value); break; case (CIRRUS_MMIO_BLTBGCOLOR + 1): cirrus_hook_read_gr(s, 0x10, &value); break; case (CIRRUS_MMIO_BLTBGCOLOR + 2): cirrus_hook_read_gr(s, 0x12, &value); break; case (CIRRUS_MMIO_BLTBGCOLOR + 3): cirrus_hook_read_gr(s, 0x14, &value); break; case (CIRRUS_MMIO_BLTFGCOLOR + 0): cirrus_hook_read_gr(s, 0x01, &value); break; case (CIRRUS_MMIO_BLTFGCOLOR + 1): cirrus_hook_read_gr(s, 0x11, &value); break; case (CIRRUS_MMIO_BLTFGCOLOR + 2): cirrus_hook_read_gr(s, 0x13, &value); break; case (CIRRUS_MMIO_BLTFGCOLOR + 3): cirrus_hook_read_gr(s, 0x15, &value); break; case (CIRRUS_MMIO_BLTWIDTH + 0): cirrus_hook_read_gr(s, 0x20, &value); break; case (CIRRUS_MMIO_BLTWIDTH + 1): cirrus_hook_read_gr(s, 0x21, &value); break; case (CIRRUS_MMIO_BLTHEIGHT + 0): cirrus_hook_read_gr(s, 0x22, &value); break; case (CIRRUS_MMIO_BLTHEIGHT + 1): cirrus_hook_read_gr(s, 0x23, &value); break; case (CIRRUS_MMIO_BLTDESTPITCH + 0): cirrus_hook_read_gr(s, 0x24, &value); break; case (CIRRUS_MMIO_BLTDESTPITCH + 1): cirrus_hook_read_gr(s, 0x25, &value); break; case (CIRRUS_MMIO_BLTSRCPITCH + 0): cirrus_hook_read_gr(s, 0x26, &value); break; case (CIRRUS_MMIO_BLTSRCPITCH + 1): cirrus_hook_read_gr(s, 0x27, &value); break; case (CIRRUS_MMIO_BLTDESTADDR + 0): cirrus_hook_read_gr(s, 0x28, &value); break; case (CIRRUS_MMIO_BLTDESTADDR + 1): cirrus_hook_read_gr(s, 0x29, &value); break; case (CIRRUS_MMIO_BLTDESTADDR + 2): cirrus_hook_read_gr(s, 0x2a, &value); break; case (CIRRUS_MMIO_BLTSRCADDR + 0): cirrus_hook_read_gr(s, 0x2c, &value); break; case (CIRRUS_MMIO_BLTSRCADDR + 1): cirrus_hook_read_gr(s, 0x2d, &value); break; case (CIRRUS_MMIO_BLTSRCADDR + 2): cirrus_hook_read_gr(s, 0x2e, &value); break; case CIRRUS_MMIO_BLTWRITEMASK: cirrus_hook_read_gr(s, 0x2f, &value); break; case CIRRUS_MMIO_BLTMODE: cirrus_hook_read_gr(s, 0x30, &value); break; case CIRRUS_MMIO_BLTROP: cirrus_hook_read_gr(s, 0x32, &value); break; case CIRRUS_MMIO_BLTMODEEXT: cirrus_hook_read_gr(s, 0x33, &value); break; case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): cirrus_hook_read_gr(s, 0x34, &value); break; case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): cirrus_hook_read_gr(s, 0x35, &value); break; case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): cirrus_hook_read_gr(s, 0x38, &value); break; case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): cirrus_hook_read_gr(s, 0x39, &value); break; case CIRRUS_MMIO_BLTSTATUS: cirrus_hook_read_gr(s, 0x31, &value); break; default:#ifdef DEBUG_CIRRUS printf("cirrus: mmio read - address 0x%04x\n", address);#endif break; } return (uint8_t) value;}⌨️ 快捷键说明
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