📄 mpc8240.h
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#define MPC8240_MCC1_ROMFAL_MASK 0x0f800000 /* ROM first access time mask */
#define MPC8240_MCC1_ROMFAL_SHIFT 23 /* ROM first access time shift*/
#define MPC8240_MCC1_DBUS_SIZE_MASK 0x00600000 /* ROM/FLASH DBUS size mask */
#define MPC8240_MCC1_64N32 0x00400000 /* 64-bit external data path */
#define MPC8240_MCC1_8N64 0x00200000 /* 8-bit ROM/Flash */
#define MPC8240_MCC1_BURST 0x00100000 /* burst mode ROM */
#define MPC8240_MCC1_MEMGO 0x00080000 /* enable RAM interface logic */
#define MPC8240_MCC1_SREN 0x00040000 /* enable self refresh */
#define MPC8240_MCC1_RAM_TYPE 0x00020000 /* RAM type: 0=SDRAM,1=FPM/EDO*/
#define MPC8240_MCC1_PCKEN 0x00010000 /* enable parity checking */
#define MPC8240_MCC1_ROW_ADRS_MASK 0x0000ffff /* row address mask */
/* Offset 0xF4 - memory control configuration #2 Register */
#define MPC8240_MCC2_TS_WAIT_TIMER_M 0xe0000000 /* ROM out disable timing */
#define MPC8240_MCC2_TS_WAIT_TIMER_S 29 /* mask and shift */
#define MPC8240_MCC2_ASRISE_MASK 0x1e000000 /* AS_ falling edge timing */
#define MPC8240_MCC2_ASRISE_SHIFT 25 /* mask and shift */
#define MPC8240_MCC2_ASFALL_MASK 0x01e00000 /* AS_ rising edge timing */
#define MPC8240_MCC2_ASFALL_SHIFT 21 /* mask and shift */
#define MPC8240_MCC2_PARITY_OR_ECC 0x00100000 /* ECC/parity mechanism */
#define MPC8240_MCC2_WR_PAR_CHK_EN 0x00080000 /* write parity check enable */
#define MPC8240_MCC2_RD_PARECC_EN 0x00040000 /* inline mem bus read parity*/
#define MPC8240_MCC2_ECCEN 0x00020000 /* ECC enable */
#define MPC8240_MCC2_EDO 0x00010000 /* EDO DRAM */
#define MPC8240_MCC2_REFINT_MASK 0x0000fffc /* refresh interval mask */
#define MPC8240_MCC2_REFINT_SHIFT 2 /* refresh interval shift */
#define MPC8240_MCC2_RSV_PG 0x00000002 /* reserve 1 page */
#define MPC8240_MCC2_RMW_PAR 0x00000001 /* parity gather/store */
/* Offset 0xF8 - memory control configuration #3 Register */
#define MPC8240_MCC3_BSTOPRE_25_M 0xf0000000 /* burst to precharge timing */
#define MPC8240_MCC3_BSTOPRE_25_S 28 /* mask and shift */
#define MPC8240_MCC3_REFREC_MASK 0x0f000000 /* refresh to active interval*/
#define MPC8240_MCC3_REFREC_SHIFT 24 /* timing mask and shift */
#define MPC8240_MCC3_RDLAT_MASK 0x00f00000 /* read data latency timing */
#define MPC8240_MCC3_RDLAT_SHIFT 20 /* mask and shift */
#define MPC8240_MCC3_CPX 0x00080000 /* CAS write timing */
#define MPC8240_MCC3_RAS6P_MASK 0x00078000 /* RAS low time for CBR */
#define MPC8240_MCC3_RAS6P_SHIFT 15 /* refresh shift and mask */
#define MPC8240_MCC3_CAS5_MASK 0x00007000 /* CAS low time for page mode*/
#define MPC8240_MCC3_CAS5_SHIFT 12 /* access mask and shift */
#define MPC8240_MCC3_CP4_MASK 0x00000e00 /* CAS precharge mask */
#define MPC8240_MCC3_CP4_SHIFT 9 /* CAS precharge shift */
#define MPC8240_MCC3_CAS3_MASK 0x000001c0 /* CAS low time for first */
#define MPC8240_MCC3_CAS3_SHIFT 6 /* data access mask and shift*/
#define MPC8240_MCC3_RCD2_MASK 0x00000038 /* RAS to CAS delay mask */
#define MPC8240_MCC3_RCD2_SHIFT 3 /* RAS to CAS delay shift */
#define MPC8240_MCC3_RP1_MASK 0x00000007 /* RAS precharge mask */
/* Offset 0xFC - memory control configuration #4 Register */
#define MPC8240_MCC4_PRETOACT_MASK 0xf0000000 /* precharge to active */
#define MPC8240_MCC4_PRETOACT_SHIFT 28 /* interval mask and shift */
#define MPC8240_MCC4_ACTOPRE_MASK 0x0f000000 /* active to precharge */
#define MPC8240_MCC4_ACTOPRE_SHIFT 24 /* interval mask and shift */
#define MPC8240_MCC4_INLINE 0x00400000 /* inline ECC/parity chk enbl*/
#define MPC8240_MCC4_REGISTERED 0x00100000 /* memory data interface */
#define MPC8240_MCC4_BSTOPRE_01_MASK 0x000c0000 /* burst to precharge timing */
#define MPC8240_MCC4_BSTOPRE_01_SHIFT 18 /* mask and shift */
#define MPC8240_MCC4_REGDIMM 0x00008000 /* config mem bus for DIMMs */
#define MPC8240_MCC4_SDMODE_CAS_SHF 12 /* CAS latency type shift */
#define MPC8240_MCC4_SDMODE_MASK 0x00007f00 /* SDRAM mode mask */
#define MPC8240_MCC4_SDMODE_SHIFT 8 /* SDRAM mode shift */
#define MPC8240_MCC4_ACTORW_MASK 0x000000f0 /* activate to read/write */
#define MPC8240_MCC4_ACTORW_SHIFT 4 /* interval mask and shift */
#define MPC8240_MCC4_BSTOPRE_69_MASK 0x0000000f /* burst to prechrg timing msk*/
/* I2C register bit definitions */
/* I2C control register */
#define MPC8240_I2C_C_MEN 0x00000080 /* module enable */
#define MPC8240_I2C_C_MIEN 0x00000040 /* module interrupt enable */
#define MPC8240_I2C_C_MSTA 0x00000020 /* master/salve mode select */
#define MPC8240_I2C_C_MTX 0x00000010 /* xmit/recv mode select */
#define MPC8240_I2C_C_TXAK 0x00000008 /* transfer acknowledge enabl */
#define MPC8240_I2C_C_RSTA 0x00000004 /* repeat start */
/* I2C status register */
#define MPC8240_I2C_S_MCF 0x00000080 /* data transfer */
#define MPC8240_I2C_S_MAAS 0x00000040 /* addressed as a slave */
#define MPC8240_I2C_S_MBB 0x00000020 /* bus busy */
#define MPC8240_I2C_S_MAL 0x00000010 /* arbitration lost */
#define MPC8240_I2C_S_SRW 0x00000004 /* slave read/write */
#define MPC8240_I2C_S_MIF 0x00000002 /* interrupt */
#define MPC8240_I2C_S_RXAK 0x00000001 /* received acknowledge */
/* EPIC register bit definitions */
/* EPIC Feature Reporting register */
#define EPIC_NIRQ 0x07ff0000 /* number of IRQs */
#define EPIC_NCPU 0x00001f00 /* number of CPUs supported */
#define EPIC_VID 0x000000ff /* version ID */
/* EPIC global configuration register */
#define EPIC_GC_RESET 0x80000000 /* reset controller */
#define EPIC_GC_MIXED 0x20000000 /* mixed mode interrupts */
/* EPIC interrupt configuration register */
#define EPIC_IC_R_MASK 0x70000000 /* clock ratio mask */
#define EPIC_IC_R_SHFT 28 /* clock ratio shift value */
#define EPIC_IC_R_VALUE 4 /* clock ratio value */
#define EPIC_IC_SIE 0x08000000 /* serial interrupt enable */
/* EPIC Vendor Identification */
#define EPIC_STEP 0x00ff0000 /* device silicon revision no. */
/* EPIC processor initialization register */
#define EPIC_PI_P0 0x00000001 /* soft reset to processor 0 */
/* EPIC global timer count register */
#define EPIC_GTC_T 0x80000000 /* toggle */
#define EPIC_GTC_C_MASK 0x7FFFFFFF /* count mask */
/* EPIC global timer base count register */
#define EPIC_GTBC_CI 0x80000000 /* count inhibit */
#define EPIC_GTBC_C_MASK 0x7FFFFFFF /* base count mask */
/* EPIC global timer vector/priority register */
#define EPIC_GTVP_M 0x80000000 /* mask interrupt */
#define EPIC_GTVP_A 0x40000000 /* interrupt requested/in-srvce */
#define EPIC_GTVP_PRI_MASK 0x000f0000 /* global timer priority mask */
#define EPIC_GTVP_PRI_0 0x00000000 /* priority 0 (disabled) */
#define EPIC_GTVP_PRI_1 0x00010000 /* priority 1 */
#define EPIC_GTVP_PRI_2 0x00020000 /* priority 2 */
#define EPIC_GTVP_PRI_3 0x00030000 /* priority 3 */
#define EPIC_GTVP_PRI_4 0x00040000 /* priority 4 */
#define EPIC_GTVP_PRI_5 0x00050000 /* priority 5 */
#define EPIC_GTVP_PRI_6 0x00060000 /* priority 6 */
#define EPIC_GTVP_PRI_7 0x00070000 /* priority 7 */
#define EPIC_GTVP_PRI_8 0x00080000 /* priority 8 */
#define EPIC_GTVP_PRI_9 0x00090000 /* priority 9 */
#define EPIC_GTVP_PRI_10 0x000a0000 /* priority 10 */
#define EPIC_GTVP_PRI_11 0x000b0000 /* priority 11 */
#define EPIC_GTVP_PRI_12 0x000c0000 /* priority 12 */
#define EPIC_GTVP_PRI_13 0x000d0000 /* priority 13 */
#define EPIC_GTVP_PRI_14 0x000e0000 /* priority 14 */
#define EPIC_GTVP_PRI_15 0x000f0000 /* priority 15 */
#define EPIC_GTVP_V_MASK 0x000000ff /* vector mask */
/* EPIC global timer destination register */
#define EPIC_GTD_P0 0x00000001 /* direct to processor 0 */
/* EPIC external/serial/dma source vector/priority registers */
#define EPIC_SRC_MASK 0x80000000 /* mask interrupt */
#define EPIC_SRC_ACT 0x40000000 /* intr requested/in-service */
#define EPIC_SRC_PLR 0x00800000 /* polarity (0/1=lo-neg/hi-pos) */
#define EPIC_SRC_SENS 0x00400000 /* sense (0/1=edge/level) */
#define EPIC_SRC_PRI_MASK 0x000f0000 /* source priority mask */
#define EPIC_SRC_PRI_0 0x00000000 /* priority 0 (disabled) */
#define EPIC_SRC_PRI_1 0x00010000 /* priority 1 */
#define EPIC_SRC_PRI_2 0x00020000 /* priority 2 */
#define EPIC_SRC_PRI_3 0x00030000 /* priority 3 */
#define EPIC_SRC_PRI_4 0x00040000 /* priority 4 */
#define EPIC_SRC_PRI_5 0x00050000 /* priority 5 */
#define EPIC_SRC_PRI_6 0x00060000 /* priority 6 */
#define EPIC_SRC_PRI_7 0x00070000 /* priority 7 */
#define EPIC_SRC_PRI_8 0x00080000 /* priority 8 */
#define EPIC_SRC_PRI_9 0x00090000 /* priority 9 */
#define EPIC_SRC_PRI_10 0x000a0000 /* priority 10 */
#define EPIC_SRC_PRI_11 0x000b0000 /* priority 11 */
#define EPIC_SRC_PRI_12 0x000c0000 /* priority 12 */
#define EPIC_SRC_PRI_13 0x000d0000 /* priority 13 */
#define EPIC_SRC_PRI_14 0x000e0000 /* priority 14 */
#define EPIC_SRC_PRI_15 0x000f0000 /* priority 15 */
#define EPIC_SRC_VEC_MASK 0x000000ff /* vector mask */
#define EPIC_SRC_POLARITY_HIGH EPIC_SRC_PLR
#define EPIC_SRC_POLARITY_LOW 0
#define EPIC_SRC_SENSE_LEVEL EPIC_SRC_SENS
#define EPIC_SRC_SENSE_EDGE 0
/* EPIC external source destination register */
#define EPIC_ESD_P0 0x00000001 /* direct to processor 0 */
/* EPIC processor current task priority register */
#define EPIC_TASK_PRI_MASK 0x0000000f /* task priority mask bits */
#define EPIC_TASK_PRI_0 0x00000000 /* priority 0 */
#define EPIC_TASK_PRI_1 0x00000001 /* priority 1 */
#define EPIC_TASK_PRI_2 0x00000002 /* priority 2 */
#define EPIC_TASK_PRI_3 0x00000003 /* priority 3 */
#define EPIC_TASK_PRI_4 0x00000004 /* priority 4 */
#define EPIC_TASK_PRI_5 0x00000005 /* priority 5 */
#define EPIC_TASK_PRI_6 0x00000006 /* priority 6 */
#define EPIC_TASK_PRI_7 0x00000007 /* priority 7 */
#define EPIC_TASK_PRI_8 0x00000008 /* priority 8 */
#define EPIC_TASK_PRI_9 0x00000009 /* priority 9 */
#define EPIC_TASK_PRI_10 0x0000000a /* priority 10 */
#define EPIC_TASK_PRI_11 0x0000000b /* priority 11 */
#define EPIC_TASK_PRI_12 0x0000000c /* priority 12 */
#define EPIC_TASK_PRI_13 0x0000000d /* priority 13 */
#define EPIC_TASK_PRI_14 0x0000000e /* priority 14 */
#define EPIC_TASK_PRI_15 0x0000000f /* priority 15 (masked) */
/* Message Unit (I2O) Register Bit Definitions */
/* Outbound Message Interrupt Status Register */
#define MPC8240_I2O_OPQI 0x00000020 /* Outbound Post Queue Intr */
#define MPC8240_I2O_ODI 0x00000008 /* Outbound Doorbell Intr */
#define MPC8240_I2O_OM1I 0x00000002 /* Outbound Message 1 Intr */
#define MPC8240_I2O_OM0I 0x00000001 /* Outbound Message 0 Intr */
/* Outbound Message Interrupt Mask Register */
#define MPC8240_I2O_OPQIM 0x00000020 /* Out Post Queue Intr Mask */
#define MPC8240_I2O_ODIM 0x00000008 /* Out Doorbell Intr Mask */
#define MPC8240_I2O_OM1IM 0x00000002 /* Outbound Msg 1 Intr Mask */
#define MPC8240_I2O_OM0IM 0x00000001 /* Outbound Msg 0 Intr Mask */
/* Inbound Message Interrupt Status Register */
#define MPC8240_I2O_OFOI 0x00000100 /* Outbound Free Ovrflw Intr */
#define MPC8240_I2O_IPOI 0x00000080 /* Inbound Post Overflow Intr */
#define MPC8240_I2O_IPQI 0x00000020 /* Inbound Post Queue Intr */
#define MPC8240_I2O_MCI 0x00000010 /* Machine Check Intr */
#define MPC8240_I2O_IDI 0x00000008 /* Inbound Doorbell Intr */
#define MPC8240_I2O_IM1I 0x00000002 /* Inbound Message 1 Intr */
#define MPC8240_I2O_IM0I 0x00000001 /* Inbound Message 0 Intr */
/* Inbound Message Interrupt Mask Register */
#define MPC8240_I2O_OFOIM 0x00000100 /* Outbound Free Ovrflw Mask */
#define MPC8240_I2O_IPOIM 0x00000080 /* Inbound Post Overflow Mask */
#define MPC8240_I2O_IPQIM 0x00000020 /* Inbound Post Queue Mask */
#define MPC8240_I2O_MCIM 0x00000010 /* Machine Check Mask */
#define MPC8240_I2O_IDIM 0x00000008 /* Inbound Doorbell Mask */
#define MPC8240_I2O_IM1IM 0x00000002 /* Inbound Message 1 Mask */
#define MPC8240_I2O_IM0IM 0x00000001 /* Inbound Message 0 Mask */
/* Inbound FIFO Pointer Registers */
#define MPC8240_I2O_IN_QBA 0xfff00000 /* Inbound Queue Base Addr */
#define MPC8240_I2O_IN_FIFO_PTR 0x000ffffc /* In FIFO pointer offset */
/* Outbound FIFO Pointer Registers */
#define MPC8240_I2O_OUT_QBA 0xfff00000 /* Outbound Queue Base Addr */
#define MPC8240_I2O_OUT_FIFO_PTR 0x000ffffc /* Out FIFO pointer offset */
/* I2O Messaging Unit Control Register */
#define MPC8240_I2O_CQS 0x0000003e /* circular queue size mask */
#define MPC8240_I2O_CQS_16K 0x00000002 /* 4K entries, 16K bytes */
#define MPC8240_I2O_CQS_32K 0x00000004 /* 8K entries, 32K bytes */
#define MPC8240_I2O_CQS_64K 0x00000008 /* 16K entries, 64K bytes */
#define MPC8240_I2O_CQS_128K 0x00000010 /* 32K entries, 128K bytes */
#define MPC8240_I2O_CQS_256K 0x00000020 /* 64K entries, 256K bytes */
#define MPC8240_I2O_CQE 0x00000001 /* circular queue enable */
/* I2O Queue Base Address Register */
#define MPC8240_I2O_QBA 0xfff00000 /* queue base address bits */
#ifdef __cplusplus
}
#endif
#endif /* INCmpc8240h */
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