syslib.c

MPC8241:本程序是freescale的824*系列的BSP源程序

/* sysLib.c - Motorola PrPMC600 board series system-dependent library */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01a,28feb00,rhk  created from version 01s, MV2100 BSP.
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c 		- Intel 8250 UART driver 
    ppcDecTimer.c 	- PowerPC decrementer timer library (system clock)
    byteNvRam.c 	- byte-oriented generic non-volatile RAM library
    pciConfigLib.c 	- PCI configuration library
    dec2155xCpci.c      - Dec/Intel non-transparent PCI-to-PCI bridge library
    mpc8240Epic.c 	- Mpc8240 Interrupt Controller
    sysMotI2c.c 	- Mpc8240 I2C interface driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/
/* includes */


#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"

#if 0
#   include "pci/pciAutoConfigLib.h"
#else
#   include "./pci/pciAutoConfigLib.h"
#endif

void sysMicroDelay(int iDelayUnit);

  
extern void useI2O(void);
/* defines */
extern int sysStartType;
#define ZERO	0

#define DEFAULT_TAS_CHECKS      10              /* rechecks for soft tas */
#define TAS_CONST               0x80
int pci1200=0;
char mac[6]={0x00,0x11,0x22,0x33,0x44,0x55};
IMPORT void * cookieArray[32];
/* structures */

typedef struct mailboxInfo
    {
    BOOL    connected;
    FUNCPTR routine;
    int     arg;
    } MAILBOX_INFO;

typedef struct mpc8240WinStruct
    {
    UINT32 winType;   /* mem or i/o */
    UINT32 winBase;   /* start of window */
    UINT32 winLimit;  /* end of window */
    } MPC8240_WIN_STRUCT;

/* The following structure is used in the support of distributed shared
 * memory interrupt sources. The structure is used to create a linked list
 * which contains an entry for each PCI device capable of generating shared
 * memory interrupts. When sysIntDisable is called with the shared memory
 * interrupt vector, the list of shared memory devices is traversed and
 * each device's intDisable routine is called to disable shared memory
 * interrupts from that device. Interrupt enable requests are handled in a
 * similar manner. The pInfo field is used to save a device-specific
 * pointer which could be used to specify the hardware's base address or
 * other similar information.
 */

typedef struct sysSmIntDevListEntry
    {
    struct sysSmIntDevListEntry * next;
    void * pInfo;
    void (* intEnable) (
                       void * pInfo,
                       UINT32 level
                       );
    void (* intDisable) (
                        void * pInfo,
                        UINT32 level
                        );
    } SYS_SM_INT_DEV_LIST_ENTRY;

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus
 * and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Local DRAM */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

#ifdef ISA_MEM_SPACE

    /* Access to PCI ISA memory space */

    {
    (void *) ISA_MSTR_MEM_LOCAL,
    (void *) ISA_MSTR_MEM_LOCAL,
    ISA_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

#endif

    /* Access to PCI non-prefetchable memory space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI memory space */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    /*{
    (void *) 0x88000000,
    (void *) 0x88000000,
    (0x8000000),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },*/
  /* Access to GALNET space */
#ifdef INCLUDE_DEVGALNET
    {
    (void *) GALNETPCIMEM,
    (void *) GALNETPCIMEM,
    GALNETMEMSIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif
#ifdef INCLUDE_PCI9030
	{
	(void *) PCI9030EXTFLASHMEM,
	(void *) PCI9030EXTFLASHMEM,
	PCI9030EXTFLASHSIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif	
    {
    /* Mpc8240 registers */
    (void *) MPC8240_EUMB_BASE,
    (void *) MPC8240_EUMB_BASE,
    MPC8240_EUMB_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
 /*	{*/
    /* Mpc8240 registers */
/*    (void *) MPC8240_PCSR_BASE,
    (void *) MPC8240_PCSR_BASE,
    4*1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },*/
    {
    /* PCI interrupt acknowledge */

    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    (void *) PCI_MSTR_IACK_WNDW_ADRS,
    PCI_MSTR_IACK_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

#ifdef CHRP_ADRS_MAP
    {

    /* PCI Configuration Address Register */

    (void *) PCI_MSTR_PRIMARY_CAR,
    (void *) PCI_MSTR_PRIMARY_CAR,
    PCI_MSTR_PRIMARY_CAR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {

    /* PCI Configuration Data Register */

    (void *) PCI_MSTR_PRIMARY_CDR,
    (void *) PCI_MSTR_PRIMARY_CDR,
    PCI_MSTR_PRIMARY_CDR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif

#ifndef CHRP_ADRS_MAP /* if PReP address map */
    {

    /* map in direct access of PCI configuration space */

    (void *) PCI_MSTR_DIRECT_MAP_ADRS,
    (void *) PCI_MSTR_DIRECT_MAP_ADRS,
    PCI_MSTR_DIRECT_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
#endif

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) 0xff000000,
    (void *) 0xff000000,
    0x1000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }

    };

UINT wbVectorIRQ0=WBPIC_INTERRUPT_BASE; /*added by xdg*/

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus      = BUS_TYPE_PCI;	/* system bus type */
int    sysCpu      = CPU;		/* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int    sysProcNum;			/* processor number of this CPU */
int    sysFlags;			/* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */

int    smIntArg1 = -1;                  /* Shared memory SM_INT_ARG1 */
int    smIntArg2 = -1;                  /* Shared memory SM_INT_ARG2 */

MPC8240_WIN_STRUCT sysMpc8240CpuToPciWin[MPC8240_WIN_CNT-1] = { { 0 } };
MPC8240_WIN_STRUCT sysMpc8240PciToCpuWin[MPC8240_WIN_CNT-1] = { { 0 } };

#ifdef INCLUDE_SM_NET
    MAILBOX_INFO sysMailbox = {FALSE, NULL, 0};
    SYS_SM_INT_DEV_LIST_ENTRY * pSmIntListHead = 0;
#endif