prpmc600.h

MPC8241:本程序是freescale的824*系列的BSP源程序

#ifdef CHRP_ADRS_MAP

/* additional PCI CHRP memory map defines (as seen from the CPU) */

#  define PCI_MSTR_PRIMARY_CAR      	0xfec00000  /* PCI config address reg */
#  define PCI_MSTR_PRIMARY_CAR_SIZE	0x00001000  /* use 4KB page tbl entry */
#  define PCI_MSTR_PRIMARY_CDR      	0xfee00000  /* PCI config data reg */
#  define PCI_MSTR_PRIMARY_CDR_SIZE	0x00001000  /* use 4KB page tbl entry */
#  define PCI_MSTR_IACK_BASE_ADRS	0xfef00000  /* PCI interrupt acknowl */
#  define PCI_MSTR_IACK_SIZE		0x00001000  /* use 4KB page tbl entry */
#  define PCI_MSTR_IACK_WNDW_ADRS	PCI_MSTR_IACK_BASE_ADRS

#else /* PReP map */

/* additional PCI PREP memory map defines (as seen from the CPU) */

#  define PCI_MSTR_PRIMARY_CAR	   (ISA_MSTR_IO_LOCAL + 0xcf8)  /* PCI CAR */
#  define PCI_MSTR_PRIMARY_CDR	   (ISA_MSTR_IO_LOCAL + 0xcfc)  /* PCI CDR */
#  define PCI_MSTR_DIRECT_MAP_ADRS (ISA_MSTR_IO_LOCAL + 0x00800000) /* base */
						    /* of direct PCI config */
						    /* space access */
#  define PCI_MSTR_DIRECT_SIZE	   0x00800000       /* 8MB */
#  define PCI_MSTR_IACK_BASE_ADRS  0xbffffff0	    /* PCI interrupt acknowl */
#  define PCI_MSTR_IACK_SIZE       0x00001000	    /* use 4KB page tbl entry */
#  define PCI_MSTR_IACK_WNDW_ADRS  0xbffff000
#  define PCI_CHRP_PRIMARY_CAR	   0xfec00000	    /* CHRP CAR and CDR adrs */
#  define PCI_CHRP_PRIMARY_CDR	   0xfee00000	    /* for switch to PReP */
#endif /* CHRP_ADRS_MAP */

/* 
 *  setup the Base Address for the Mpc8240 registers, use the 1MB block
 *  just below the top of PCI Memory space.
 */

#ifdef CHRP_ADRS_MAP
#  define MPC8240_REGISTERS_BASE	0xfcf00000/*0xa0000000*/
#else
#  define MPC8240_REGISTERS_BASE	0xfef00000
#endif /* CHRP_ADRS_MAP */

#define FLASH_BASE_ADRS         0x70000000/*0xff000000*/
#define FLASH_MEM_SIZE          0x01000000    /*16M bytes*/

/* defines for PCI AUTO_CONFIG */

#define ISA_LEGACY_SIZE 	0x00004000

/*
 * PCI MASTER MEMORY WINDOW LIMITS for sysBusProbe
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks for the PCI bus to work properly.
 */

#define PCI_MSTR_MEM_LO_ADRS	PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEM_HI_ADRS	(PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)
#define PCI_MSTR_IO_LO_ADRS	ISA_MSTR_IO_LOCAL
#define PCI_MSTR_IO_HI_ADRS	(PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE)

/* 
 * Map PCI memory access to local CPU space
 *
 * PCI_SLV_MEM_LOCAL  - Base address of Local CPU space
 * PCI_SLV_MEM_BUS    - Base address of local memory as seen from PCI Bus
 * PCI_SLV_MEM_SIZE   - Size of Window for Local space access
 */

/*
 * The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of
 * local memory.  A PCI memory device that puts this address onto the bus will
 * access local memory at the address specified by PCI_SLV_MEM_LOCAL
 */

#ifdef CHRP_ADRS_MAP
#  define PCI_SLV_MEM_BUS	0x00000000
#else /* PReP map */
#  define PCI_SLV_MEM_BUS       0x80000000
#endif /* CHRP_ADRS_MAP */

#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS	 /* needed for usrNetwork.c */

/*
 * The macro PCI_SLV_MEM_LOCAL is the base at which local memory will appear
 * in CPU space.
 */

#define PCI_SLV_MEM_LOCAL       LOCAL_MEM_LOCAL_ADRS

/*
 * The macro PCI_SLV_MEM_SIZE specify the range of PCI
 * memory space as it appears on the PCI bus.
 */

#ifdef CHRP_ADRS_MAP
#  define PCI_SLV_MEM_SIZE	0x40000000	/* CHRP max is 1 GB */
#else /* PReP map */
#  define PCI_SLV_MEM_SIZE      0x80000000      /* PReP max is 2GB */
#endif /* CHRP_ADRS_MAP */

/* PCI device select definitions */

#define PCI_DEVSEL_PHB           0       	/* Mpc8240 PCI host bridge */
#define PCI_DEVSEL_ETHERNET      14      	/* DEC21143 Ethernet */
#define PCI_DEVSEL_PCMIPT1S1     16      	/* PC-MIP Type 1 Slot 1 (PMC) */
#define PCI_DEVSEL_PCMIPT1S2     17      	/* PC-MIP Type 1 Slot 2 */
#define PCI_DEVSEL_PCMIPT2S1     18      	/* PC-MIP Type 2 Slot 1 */
#define PCI_DEVSEL_PCMIPT2S2     19      	/* PC-MIP Type 2 Slot 2 */


/*
 * PCI Config Space device addresses based on their device number
 *
 * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles
 */

#define CNFG_START_SEARCH	0x5800     /* PCI Space starting offset */
#define CNFG_PCI_HOST_BRDG	0x80000000 /* Mpc8240 PCI host bridge */
#define CNFG_IBC_ADRS		0x80005800 /* IBC */
#define CNFG_SCSI_ADRS		0x80006000 /* SCSI */
#define CNFG_LN_ADRS		0x80007000 /* Ethernet Device */
#define CNFG_VGA_ADRS		0x80007800 /* Graphics Device */
#define CNFG_PCMIPT1S1_ADRS     0x80008000 /* PC-MIP Type 1 Slot 1 (PMC) */
#define CNFG_PCMIPT1S2_ADRS     0x80008800 /* PC-MIP Type 1 Slot 2 */
#define CNFG_PCMIPT2S1_ADRS     0x80009000 /* PC-MIP Type 2 Slot 1 */
#define CNFG_PCMIPT2S2_ADRS     0x80009800 /* PC-MIP Type 2 Slot 2 */
     
/* Special dec21143 configuration device driver area register */

#define PCI_CFG_21143_DA	0x40

/* Number of PCI devices */

#define NUM_PCI_DEVS		4

/* PCI Device/Vendor IDs */

#define PCI_ID_LN_DEC21140      0x00091011      /* Id DEC chip 21140 */
#define PCI_ID_LN_DEC21143      0x00191011      /* Id DEC chip 21143 */
#define PCI_ID_LN_I82559ER	0x12098086	/* Id for I82559ER chip */
#define PCI_ID_LN_I82559	0x12298086      /* Id for Intel 82559 */
#define PCI_ID_SCSI             0x00031000      /* Id for SYM53C825/75 Chips */
#define PCI_ID_SEC_SCSI         0x00011000      /* Id for SYM53C810A Chip */
#define PCI_ID_NCR810           0x00011000      /* Id for SYM53C810A Chip */
#define PCI_ID_NCR860           0x00061000      /* Id for SYM53C860 Chip */
#define PCI_ID_NCR825           0x00031000      /* Id for SYM53C825/75 Chips*/
#define PCI_ID_LN_DEC21040      0x00021011      /* Id DEC chip 21040 */
#define PCI_ID_5434             0x00a81013      /* Id for CL-GD534 chip */
#define PCI_ID_5436             0x00ac1013      /* Id for CL-GD536 chip */
#define PCI_ID_BR_DEC21150      0x00221011      /* Id DEC 21150 PCI bridge */
#define PCI_ID_MPC8240_CFG	0x00031057	/* Id for Mpc8240 config regs */
#define PCI_ID_BR_DEC21554      0x00461011      /* Id DEC 21554 PCI bridge */
#define PCI_ID_UNIVERSE         0x000010e3      /* Id for Universe VME chip */
#define PCI_ID_HAWK             0x48031057      /* Id for HAWK PHB */
#define PCI_ID_IBC              0x05861106      /* Id for VT82586 PBC */
#define PCI_ID_IDE              0x05711106      /* Id for VT82586 IDE */
/* the following one line is add by xdg */
#define PCI_ID_W83C553			0x056510ad		/* Id for PCI/ISA bridge in W83C553 */

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
#  define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
#  define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif

/*
 * Allocate PCI Memory and I/O Space Offsets for PCI devices
 *
 * All devices on the primary and secondary busses are allocated 64 kb spaces.
 * The PMC Span can control up to four PMCs.
 */

#define SCSI_DEV_SPACE          0x10000
#define LAN_DEV_SPACE           0x20000
#define VGA_DEV_SPACE           0x30000
#define PMC_DEV_SPACE           0x40000
#define LAN2_DEV_SPACE          0x60000
#define SCSI_DEV_SPACE2         0x70000
#define SPAN_IO_DEV_SPACE       0x80000
#define SPAN_IO_DEV_SIZE        0x40000
#define SPAN_MEM_DEV_SPACE      0x02000000
#define SPAN_MEM_DEV_SIZE       0x01000000
#define SPAN_PREF_DEV_SPACE     0x01000000
#define SPAN_PREF_DEV_SIZE      0x01000000

/* PCI view of PCI I/O Space for PCI devices */

#define PCI_IO_SCSI_ADRS        (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE)  /* 53C825 */
#define PCI_IO_LN_ADRS          (PCI_MSTR_IO_BUS + LAN_DEV_SPACE)   /* PCnet */
#define PCI_IO_VGA_ADRS         (PCI_MSTR_IO_BUS + VGA_DEV_SPACE)   /* GD5434 */
#define PCI_IO_PMC_ADRS         (PCI_MSTR_IO_BUS + PMC_DEV_SPACE)   /* extra */
#define PCI_IO_LN2_ADRS         (PCI_MSTR_IO_BUS + LAN2_DEV_SPACE)  /* 21040  */
#define PCI_IO_SCSI_ADRS2       (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE2) /* 53C825A*/

/* Allocated base address of HW devices as seen from CPU */

#define SCSI_BASE_ADRS          ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE )
#define LAN_BASE_ADRS           ( PCI_MSTR_IO_LOCAL + LAN_DEV_SPACE )
#define LAN2_BASE_ADRS          ( PCI_MSTR_IO_LOCAL + LAN2_DEV_SPACE )
#define SCSI_BASE_ADRS2         ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE2 )

/* 
 * System I/O address definitions
 *
 * The system resources are mapped into the lower 1MB address
 * range of FLASH/ROM bank 0 (FFE00000 - FFEFFFFF).
 */

#define PRPMC600_SIO_BASE		0xFFE00000     /* base address of system I/O */
#define PRPMC600_SIO_SIZE		0x00100000     /* base address of system I/O */

#define PRPMC600_SYS_STAT_REG1	(PRPMC600_SIO_BASE+0x00000) 
#define PRPMC600_SYS_STAT_REG2	(PRPMC600_SIO_BASE+0x01000)
#define PRPMC600_CONFIG_HDR_REG   (PRPMC600_SIO_BASE+0x04000)
#define PRPMC600_COM1_UART	(PRPMC600_SIO_BASE+0x10000)

/* Bit masks and bit definitions for system status register #1 */

#define PRPMC600_RESET		0x80	/* hard reset of prpmc600 board */
#define PRPMC600_MONARCH	0x40    /* if set prpmc600 is in slave mode */
#define PRPMC600_ABORT		0x10	/* state of the abort signal */
#define PRPMC600_EEPROM_WP	0x08	/* EEPROM write protect bit */
#define PRPMC600_FLASH_WP	0x04	/* INTEL only, FLASH write protect */
#define PRPMC600_FLASH_BSY	0x02	/* AMD only, FLASH device busy */
#define PRPMC600_REF_CLK	0x01	/* reference clock */
#define PRPMC600_REF_CLK_BIT	0x00	/* reference clock bit position */

/* bit masks for system status register #2 */

#define PRPMC600_BD_FAIL	0x80	/* Board fail indicator */
#define PRPMC600_LED_1		0x40	/* LED  1 bit, for future use */
#define PRPMC600_LED_2          0x20	/* LED  2 bit, for future use */
#define PRPMC600_LED_3          0x10    /* LED  3 bit, for future use */
#define PRPMC600_LED_4          0x08    /* LED  4 bit, for future use */

/* Configuration Header register bit masks */

#define PRPMC600_CFG3           0x10    /* 0 = jumper in header position 7-8 */
#define PRPMC600_CFG2           0x20    /* 0 = jumper in header position 5-6 */
#define PRPMC600_CFG1           0x40    /* 0 = jumper in header position 3-4 */
#define PRPMC600_CFG0		0x80	/* 0 = jumper in header position 1-2 */
#define BUS_SPEED_MASK 		0xF8

/* programmable interrupt controller (PIC) */

#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* programmable interrupt timers */

#define PIT_BASE_ADR		SL82565_TMR1_CNT0	/* timeraddrs */
#define PIT_REG_ADDR_INTERVAL	1
#define PIT_CLOCK		1193180

/* PC97307 UART1&2 added by xdg, 00.10.16*/
#define NS_COM1_ADR        	0x03f8		/* Serial port com1 of PC97307*/
#define NS_COM2_ADR        	0x02f8		/* Serial port com2 of PC97307*/
#define NS_COM1_BASE_ADR_DYN	(ISA_MSTR_IO_LOCAL + NS_COM1_ADR)
#define NS_COM2_BASE_ADR_DYN	(ISA_MSTR_IO_LOCAL + NS_COM2_ADR)

/* serial ports (COM) */
/*#define PMC_COM_ADR        0xff900000*//*0xFFF80008*/
#define PMC_COM_ADR	       (MPC8240_EUMB_BASE + 0x4500)
#define COM1_BASE_ADR		PMC_COM_ADR  /* serial port 1 */
#define PMC_COM_SIZE	0x00001000
/* PC97307 UART1&2 added by xdg, 00.10.16*/
#define COM2_BASE_ADR		(MPC8240_EUMB_BASE + 0x4600) /* serial port 2 */ /* modified by zoutl 2003-3-28 17:32 */
#define COM3_BASE_ADR		NS_COM2_BASE_ADR_DYN  /* serial port 3 */
#define UART_REG_ADDR_INTERVAL  1       	  /* addr differential */
#define N_UART_CHANNELS 	1		  /* No. serial I/O chans should be 3, xdg */  /* uart2 */
#define N_SIO_CHANNELS          N_UART_CHANNELS   /* No. serial I/O chans */

#define NV_RAM_READ(x)		sysNvRead (x)
#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)

/* Dec2155x (Drawbridge) related defines */

#define DEC2155X_MAILBOX_INT_VEC (DEC2155X_DOORBELL0_INT_VEC + \
                                  DEC2155X_SM_DOORBELL_BIT)
#ifdef INCLUDE_DEC2155X


#   define DEC2155X_BIST_VAL         0x00
#   define DEC2155X_PRI_PRG_IF_VAL   0x00
#   define DEC2155X_PRI_SUBCLASS_VAL 0x20
#   define DEC2155X_PRI_CLASS_VAL    0x0b
#   define DEC2155X_SEC_PRG_IF_VAL   0x00
#   define DEC2155X_SEC_SUBCLASS_VAL 0x80
#   define DEC2155X_SEC_CLASS_VAL    0x06
#   define DEC2155X_MAX_LAT_VAL      0x00