prpmc600.h

MPC8241:本程序是freescale的824*系列的BSP源程序

/* prpmc600.h - Motorola PowerPlus board header */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01d,21jun00,rhk  fixed the constant NUM_SDRAM_BANKS for memory mezz. support.
01c,06jun00,rhk  code format changes.
01b,10may00,rhk  added Drawbridge support.
01a,25feb00,rhk  created. (from ver 01p, mv2100.h)
*/

/*
This file contains I/O addresses and related constants for the
Motorola PrPMC600 PowerPlus board. 
*/

#ifndef	INCprpmc600h
#define	INCprpmc600h

#ifdef __cplusplus
    extern "C" {
#endif

#include "mpc8240.h"

/* CPU type */

#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601		0x01		/* PPC 601 CPU */
#define CPU_TYPE_602		0x02		/* PPC 602 CPU */
#define CPU_TYPE_603		0x03		/* PPC 603 CPU */
#define CPU_TYPE_603E       0x06   		/* PPC 603e CPU */
#define CPU_TYPE_603EK		0x81		/* PPC 603e-Mpc8240 CPU */
#define CPU_TYPE_603P       0x07    	/* PPC 603p CPU */
#define CPU_TYPE_750        0x08    	/* PPC 750 CPU */
#define CPU_TYPE_604		0x04		/* PPC 604 CPU */
#define CPU_TYPE_604E		0x09		/* PPC 604e CPU */
#define CPU_TYPE_604R		0x0A		/* PPC 604r CPU */
#define CPU_TYPE_8245		0x8081		/* PPC 603e-Mpc8240 CPU */

/* Vital Product Data Support */

#define NUM_SDRAM_BANKS		6	/* max pssible SDRAM banks, mult of 2 */
#define SPD_EEPROM_ADRS0	0xa0	/* i2c address of first SPD EEPROM */
#define VPD_BRD_EEPROM_ADRS	0xa2	/* i2c address of board's SROM */
#define USR_SROM_ADRS		0xa4	/* i2c addr. of user configured SROM */
#define USR_SROM_SIZE		256
#define HOST_BRD_CONFIG		0xa6	/* optional host board configuration */
#define MEM_MEZZ_23		0xaa	/* mem. mezzanine SPD banks 2/3 */
#define MEM_MEZZ_45		0xac	/* mem. mezzanine SPD banks 4/5 */
#define VPD_BRD_OFFSET		0	/* offset into board's eeprom for 
					  			   vpd data */
#define EEPROM_TYPE_MPC8240	0
#define I2C_DRV_TYPE		EEPROM_TYPE_MPC8240 /* I2C driver type flag */
#define VPD_PKT_LIMIT		25	/* Max number of packets expected */

#define DEFAULT_PCI_CLOCK	33333333

#define DEFAULT_BUS_CLOCK	66700000 /*by wanggeng 20050803*/
/* #define DEFAULT_BUS_CLOCK	100000000 *//* modify by zoutl for 100M */
#define DEFAULT_INTERNAL_CLOCK	250000000
#define DEFAULT_BUS_CLOCK100	100000000
#define DEFAULT_PRODUCT_ID	"Unknown"

#define MHZ	    		1000000
#define NANO2SEC    		1000000000  /* num of nanoseconds per second */

#define INCLUDE_PCI		/* always include pci */

#define MPC8240_WIN_CNT		5	/* num. CPU - PCI translation windows */

/* Boot Line parameters are stored in the user SROM */

#define NV_RAM_SIZE    		USR_SROM_SIZE

/* PCI I/O function defines */

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)	  sysPciInByte (x)
    IMPORT  UINT8                 sysPciInByte  (UINT32 address);
#endif
#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)         sysPciInWord (x)
    IMPORT  UINT16                sysPciInWord  (UINT32 address);
#endif
#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)         sysPciInLong (x)
    IMPORT  UINT32                sysPciInLong  (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)      sysPciOutByte (x,y)
    IMPORT  void                  sysPciOutByte (UINT32 address, UINT8  data);
#endif
#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)      sysPciOutWord (x,y)
    IMPORT  void                  sysPciOutWord (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)      sysPciOutLong (x,y)
    IMPORT  void                  sysPciOutLong (UINT32 address, UINT32 data);
#endif
#ifndef PCI_INSERT_LONG
#   define PCI_INSERT_LONG(a,m,d) sysPciInsertLong((a),(m),(d))
    IMPORT  void                  sysPciInsertLong(UINT32 adrs, UINT32 mask, \
                                                   UINT32 data);
#endif
#ifndef PCI_INSERT_WORD
#   define PCI_INSERT_WORD(a,m,d) sysPciInsertWord((a),(m),(d))
    IMPORT  void                  sysPciInsertWord(UINT32 adrs, UINT16 mask, \
                                                   UINT16 data);
#endif
#ifndef PCI_INSERT_BYTE
#   define PCI_INSERT_BYTE(a,m,d) sysPciInsertByte((a),(m),(d))
    IMPORT  void                  sysPciInsertByte(UINT32 adrs, UINT8 mask, \
                                                   UINT8 data);
#endif

#endif  /* _ASMLANGUAGE */

/* Cache Line Size -  8 32-bit words = 32 bytes */

#define PCI_CLINE_SZ		(_CACHE_ALIGN_SIZE/4)

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

#define SPEED66MHZ		66
#define SPEED83MHZ		83
#define SPEED100MHZ		100

/* memory refresh loop constant */

#define WAIT_REFRESH_COUNT	2083 

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED        (sysGetBusSpdHertz())

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ          MEMORY_BUS_SPEED

/* CIO clocks and stuff */

#define	CIO_RESET_DELAY		5000
#define	ZCIO_HZ			2500000 /* 2.5 MHz clock */
#define	CIO_INT_VEC		9
#define	Z8536_TC		ZCIO_HZ

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate */

/*
 * This macro returns the positive difference between two signed ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)		( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	100000		/* max auxiliary clock rate */ /* modify by zoutl 5000->100000 */

/*
 * Common I/O synchronizing instructions
 *
 * Only SYNC is used for the 603e processors.  The "eieio" instruction
 * is treated as a NOP on the 603e.
 */

#ifndef SYNC
#  define SYNC                  __asm__ volatile ("sync")
#endif  /* SYNC */

#ifndef EIEIO_SYNC
# define EIEIO_SYNC  __asm__(" isync; sync")
#endif /*EIEIO_SYNC*/
/* Translation macro */

#define TRANSLATE(x,y,z)\
        ((UINT)(x) - (UINT)(y) + (UINT)(z))

/* BSP configuration error policy */

#define CONTINUE_EXECUTION      0       /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR  1       /* Transfer to System Monitor */

#ifdef TOLERATE_CONFIG_ERRORS
#  define DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION
#else
#  define DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR
#endif

/* 
 * The following macros define access to PCI and ISA space from the CPU
 * and the base addresses of PCI and ISA spaces on the bus (from the CPU
 * point of view).
 * These macros contain the correct starting addresses and sizes
 * for use in the BSP and user programming.
 *
 */

#ifdef CHRP_ADRS_MAP

/* Access to PCI ISA I/O space */

#  define ISA_MSTR_IO_LOCAL	0xfe000000
#  define ISA_MSTR_IO_BUS	0x00000000              /* 0 based addressing */
#  define ISA_MSTR_IO_SIZE 	0x00010000              /* 64 kbytes max. */

/* Access to PCI I/O space */

#  define PCI_MSTR_IO_LOCAL	0xfe800000
#  define PCI_MSTR_IO_BUS	0x00800000		
#  define PCI_MSTR_IO_SIZE	0x00400000		/* 4MB max. */

/* Access to PCI ISA memory space (legacy space) */

#  ifdef ISA_MEM_SPACE
#    define ISA_MSTR_MEM_LOCAL	0xfd000000
#    define ISA_MSTR_MEM_BUS	0x00000000		/* 0 based addressing */
#  endif

/* Access to PCI nonprefetchable memory space (including ISA memory space) */

#  define PCI_MSTR_MEMIO_LOCAL  0x80000000
#  define PCI_MSTR_MEMIO_BUS    PCI_MSTR_MEMIO_LOCAL    /* 1-1 translation */

/* Access to PCI memory space (prefetchable) */

#  define PCI_MSTR_MEM_LOCAL    (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#  define PCI_MSTR_MEM_BUS      PCI_MSTR_MEM_LOCAL      /* CHRP mode uses */
							/* pass through addr */

#else /* PReP map */

/* Access to PCI ISA I/O space */

#  define ISA_MSTR_IO_LOCAL   	0x80000000
#  define ISA_MSTR_IO_BUS     	0x00000000              /* 0 based addressing */
#  define ISA_MSTR_IO_SIZE 	0x00010000              /* 64 kbytes max. */

/* Access to PCI I/O space */

#  define PCI_MSTR_IO_LOCAL     0x81000000
#  define PCI_MSTR_IO_BUS       0x01000000              /* 0 base + ISA range */

/* Access to PCI ISA memory space (legacy space) */

#  ifdef ISA_MEM_SPACE
#    define ISA_MSTR_MEM_LOCAL  0xc0000000
#    define ISA_MSTR_MEM_BUS    0x00000000              /* 0 based addressing */
#  endif

/* Access to PCI nonprefetchable memory space (including ISA memory space) */

#  define PCI_MSTR_MEMIO_LOCAL  0xc1000000
#  define PCI_MSTR_MEMIO_BUS    0x01000000              /* 0 based addressing */

/* Access to PCI memory space */

#  define PCI_MSTR_MEM_LOCAL    (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#  define PCI_MSTR_MEM_BUS      (PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE)

#endif /* CHRP_ADRS_MAP */

/* 
 * The following describes the additional address spaces used for 
 * PCI space configuration on the Mpc8240 processor.  The addresses 
 * for each type of mapping (CHRP or PReP) are fixed and cannot be
 * modified.
 */