rominit.s

MPC8241:本程序是freescale的824*系列的BSP源程序

/* romInit.s - Motorola PRPMC600 ROM initialization module */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01b,02jun00,rhk  modified the default setup values for the MCCR registers.
01a,28feb00,rhk  created from version 01h, MV2100 BSP.
modify by msy 3/4 2002
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"	

	/* Exported internal functions */
	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */

	/* externals */

	.extern romStart	/* system initialization routine */
	.extern	mpc8240DefInit   /* default memory initialization */
	.extern	waitRefresh 
	.extern	SdramTest

	.text
	.align 2

		
/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )
*/
/*.space (0x100)*/
_romInit:
romInit:

	bl	cold
	nop
	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1999 Wind River Systems, Inc."
	.align 2

cold:
	li	r31, BOOT_COLD
	bl	start		/* skip over next instruction */
			
warm:
	or	r31, r3, r3	/* startType to r31 */

start:
	xor     r0,r0,r0
	mtspr   272,r0
	mtspr   273,r0
	mtspr   274,r0
	mtspr   275,r0

    /* initialize the stack pointer */
    lis     sp, HI(STACK_ADRS)
    ori     sp, sp, LO(STACK_ADRS)

	/*
	 *	Set HID0 to a known state
	 *	Enable machine check input pin (EMCP) for DRAM ECC detection
	 */
	addis   r3,r0,0x8000
	ori     r3,r3,0x0000
	mtspr   HID0, r3

	xor     r3, r3, r3		/* clear r3 */

	/* Turn on FPU if enabled and available */

    mfspr   r3, 1009		/* load hid1 contents */
    andi.   r3, r3, 0x0001		/* extract FPU available bit and test */
    bc      4,2,skipFpuInit		/* if not equal, then we have no FPU */
	xor     r3, r3, r3		/* clear r3 */
    ori     r3, r3, 0x2000		/* set FP */
    isync				/* synchronize */
    mtmsr   r3			/* set machine state register */
    isync				/* synchronize */

	/* Init the floating point control/status register */

	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync
        bl       dontTurnOffFP
skipFpuInit:

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn off FP
	 */

	
	/* addi	r3, r0, 0xb930 */ /* modify by zoutl */
	ori	r3, r0, 0xb930
	isync
	mtmsr 	r3
	isync

dontTurnOffFP:
	/* Init the Segment registers */

	andi.	r3, r3, 0
	isync
	mtsr    0,r3
	isync
	mtsr    1,r3
	isync
	mtsr    2,r3
	isync
	mtsr    3,r3
	isync
	mtsr    4,r3
	isync
	mtsr    5,r3
	isync
	mtsr    6,r3
	isync
	mtsr    7,r3
	isync
	mtsr    8,r3
	isync
	mtsr    9,r3
	isync
	mtsr    10,r3
	isync
	mtsr    11,r3
	isync
	mtsr    12,r3
	isync
	mtsr    13,r3
	isync
	mtsr    14,r3
	isync
	mtsr    15,r3
	isync

	cmpli   0,0,r31,BOOT_COLD	/* check for warm boot */
	bc	4,2,skipMemGo		/* if warm boot, skip mem cntlr init */

	/* Clear MEMGO in MCCR1 so we can make memory controller adjustments. */

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori		r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,MPC8240_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */
	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori		r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori		r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(MPC8240_MCC1_MEMGO)
	ori		r3,r3,LO(MPC8240_MCC1_MEMGO)
	andc	r5,r5,r3		/* and in complement of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

    /* 
     * Configure the memory controller in a default setting so that
     * we can create a stack and read the SPD/VPD data.
     */

	bl	mpc8240DefInit		/* (mpc8240DefInit) */
	
	/* add by zoutl for double boot */	
	/*  xor		r3,r3,r3		
	 *  xor		r4,r4,r4		
	 *  addi    r4,r4,0x0007  
	 *  oris	r4,r4,0xff00	
	 *  addi    r3,r3,0x0080  
	 *  oris	r3,r3,0x0000		
         *  stb     r3,0(r4) 
         */    
    	
    
    /* 点运行灯表明桥片已经初始化成功 */    
   /* xor		r3,r3,r3		
    *	xor		r4,r4,r4		
    *   addi    r4,r4,0x0000  
    *   oris	r4,r4,0xff00	
    *   lbz     r3,0(r4)
    *   ori     r3,r3,0x0018	
    *   oris	r3,r3,0x0000		
    *   stb     r3,0(r4)         
    */
    /* 进行SDRAM测试，如果失败点告警灯 2002-4-22 16:42 */
    /* bl      SdramTest */
    
	/* Enable Instruction Cache */

	mfspr   r4, HID0		/* r4 = default */
	isync

/*	addi	r4, r0, 0x1800	*/	/* preprocessor work-around (0x8800) */
/*	addi	r4, r4, 0x7000	*/	/* r4 = ICE & ICFI bit */
	ori		r4, r4, 0x8800	

    mtspr   HID0, r4        /* HID0 = Enable/Inval IC */
	isync

	addi	r3, r0, 0x0800		/* r3 = ICFI bit */
	andc	r4, r4, r3		    /* r4 = clear ICFI bit */

    mtspr   HID0, r4            /* HID0 = Enable IC */
	isync

     /* Wait for memory refresh to occur. */

    bl	waitRefresh
    b	skipMemGo   /*goCEntry*/	/* error, leave default mem cnfg */

skipMemGo:
	/* Turn off data and instruction cache control bits */
	
	mfspr   r3, HID0
	isync
	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
	sync
	isync
	mtspr	HID0, r4		/* HID0 = r4 data/instr cache disabld */
	isync

#ifdef USER_I_CACHE_ENABLE 

	/* turn the Instruction cache ON for faster ROM access */

	mfspr   r4, HID0

	ori		r4, r4, 0x8800		/* set ICE & ICFI bit */
    mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */
	isync

    /*
     * The setting of the instruction cache enable (ICE) bit must be
     * preceded by an isync instruction to prevent the cache from being
     * enabled or disabled while an instruction access is in progress.
     */
    rlwinm  r3, r4, 0, 21, 19	/* clear the ICFI bit */
    mtspr   HID0, r3                /* using 2 consec instructions */
	isync
#endif

#ifdef INCLUDE_ECC
     cmpli   0,0,r31,BOOT_COLD	/* check for warm boot */
     bc	4,2,goCEntry		/* if warm boot, skip scrub */

	/* Scrub memory and initialize ECC */

	addis	r3,r0,0x0000		/* memory starting address */
	ori	r3,r3,0x0000		/* memory starting address */
	add	r4,r3,r29		/* memory ending address + 1 */
	bl	mpc8240Scrub		/* (mpc8240Scrub) */

#endif /* INCLUDE_ECC */


	/* 闪灯并灭掉表明跑过汇编代码 */
#if (0)
	addis    r4,0,0xFF00	
    addis     r5,0,0x0000
	ori       r5,r5,0x0000   

alloop:        
    addis      r3,0,0x0000
    stw      r3,0x0(r4) 
	addis	r6,0,0x0400 /* 0x0400-->0x4000 modify by zoutl 2003-5-22 14:28 */
	mtspr	CTR,r6	
	eieio
	sync
write1_loop:
	eieio
	bc	16,0,write1_loop	
	addis      r3,0,0x0300
    stw      r3,0x0(r4)
	addis	r6,0,0x0400 /* 0x0400-->0x4000 modify by zoutl 2003-5-22 14:28 */
	mtspr	CTR,r6	
	eieio
	sync
write_loop:
	eieio
	bc	16,0,write_loop	
	eieio
	sync	
#endif	

goCEntry:
	/* go to C entry point */

	or	r3, r31, r31
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

    lis     r6, HI(romStart)
    ori	r6, r6, LO(romStart)

    lis     r7, HI(romInit)
    ori	r7, r7, LO(romInit)

    lis     r8, HI(ROM_TEXT_ADRS)
    ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6
	blr