sysalib.s

MPC8241:本程序是freescale的824*系列的BSP源程序

        bclr    20,0                    /* return to caller */

/*****************************************************************************
*
* sysPciConfigOutLong - writes a longword to a PCI configuration space address.
*
* This function writes a longword to a specified PCI configuration space
* address.  This function uses the indirect PCI configuration space access
* method.  It writes the input configuration space address to the CAR and
* then writes the data to the CDR.  All writes larger than 8 bits use byte
* swapping.
*
* Register Usage
* r3 - Configuration space address to write to
* r4 - data to be written
* r5 - dummy parameter, used for holding the CAR address
* r6 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* void sysPciConfigOutLong (UINT32 * dataPtr, UINT32 data,UINT dummy1,UINT dummy2)
*/

sysPciConfigOutLong:

        addis   r5,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
        ori     r5,r5,LO(PCI_MSTR_PRIMARY_CAR)
        addis   r6,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
        ori     r6,r6,LO(PCI_MSTR_PRIMARY_CDR)
        stwbrx  r3,r0,r5                /* write config. space addr. to CAR */
        sync                            /* ensure memory access is complete */
        stwbrx	r4,r0,r6                /* write data to CDR */
        sync                            /* ensure memory access is complete */
        bclr    20,0                    /* return to caller */


/*******************************************************************************
*
* sysMemProbeSup - sysBusProbe support routine
*
* This routine is called to try to read byte, word, or long, as specified
* by length, from the specified source to the specified destination.
*
* RETURNS: OK if successful probe, else ERROR

STATUS sysMemProbeSup (length, src, dest)
    (
    int         length, // length of cell to test (1, 2, 4, 8, 16) *
    char *      src,    // address to read *
    char *      dest    // address to write *
    )

*/

sysMemProbeSup:
        addi    p7, p0, 0       /* save length to p7 */
        xor     p0, p0, p0      /* set return status */
        cmpwi   p7, 1           /* check for byte access */
        bne     sbpShort        /* no, go check for short word access */
        lbz     p6, 0(p1)       /* load byte from source */
        stb     p6, 0(p2)       /* store byte to destination */
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sbpShort:
        cmpwi   p7, 2           /* check for short word access */
        bne     sbpWord         /* no, check for word access */
        lhz     p6, 0(p1)       /* load half word from source */
        sth     p6, 0(p2)       /* store half word to destination */
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sbpWord:
        cmpwi   p7, 4           /* check for short word access */
        bne     sysProbeExc     /* no, check for double word access */
        lwz     p6, 0(p1)       /* load half word from source */
        stw     p6, 0(p2)       /* store half word to destination */
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sysProbeExc:
        li      p0, -1          /* shouldn't ever get here, but... */
        blr

/******************************************************************************
*
* sysTimeBaseLGet - Get lower half of Time Base Register
*
* This routine will read the contents the lower half of the Time
* Base Register (TBL - TBR 268).
*
* From a C point of view, the routine is defined as follows:
*
*    UINT32 sysTimeBaseLGet(void)
*
* RETURNS: value of TBR 268 (in r3)
*/

sysTimeBaseLGet:
	mftb 3
	bclr 20,0

/******************************************************************************
*
* sysHid0Get - read from HID0 register SPR1009.
*
* This routine will return the contents of the HID0 (SPR1008)
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid0Get()
*
* RETURNS: value of SPR1008 (in r3)
*/

sysHid0Get:
	mfspr r3,1008
	bclr 20,0



/******************************************************************************
*
* sysHid1Get - read from HID1 register SPR1009.
*
* This routine will return the contents of the HID1 (SPR1009)
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid1Get()
*
* RETURNS: value of SPR1009 (in r3)
*/

sysHid1Get:
	mfspr r3,1009
	bclr 20,0

/******************************************************************************
*
* sysHid2Get - read from HID2 register SPR1011.
*
* This routine will return the contents of the HID2 (SPR1011)
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid2Get()
*
* RETURNS: value of SPR1011 (in r3)
*/

sysHid2Get:
        mfspr r3,1011
        bclr 20,0

/******************************************************************************
*
* sysHid2Set - write data to HID2 register SPR1011.
*
* This routine will store the contents of HID2 (SPR1011) with the data
* supplied in R3.
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid2Set(UINT dataValue)
*
* RETURNS: N/A
*/

sysHid2Set:
        mtspr 1011,r3
        bclr 20,0





/*add for test

UINT32 sysMpc8240GetDec(void)

*/
sysMpc8240GetDec:
	mfspr 3,22;	/* read the decrementer */
    bclr 20,0;	/* Here's the actual return */



/*****************************************************************************
*UINT32 i2cPciInLong (UINT32 * dataPtr)
*
* i2cPciInLong - reads a longword from PCI I/O or Memory space
*
* This function reads a longword from a specified PCI I/O or Memory address
* via the PCI bridge chip.  This function should be used for access
* to the I/O or Memory mapped registers of a PCI device.  These
* registers are mapped as little-endian, so we byte reverse the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: longword from address.
*
*/
i2cPciInLong:
   lwbrx    3,0,3;
   bclr 20,0;	/* Here's the actual return */
   
   
/*****************************************************************************
*UINT8 i2cPciInByte (UINT8 * dataPtr)
*
* i2cPciInByte - reads a byte from PCI I/O or Memory space
*
* This function reads a byte from a specified PCI I/O or Memory address
* via the PCI bridge chip.  This function should be used for access
* to the I/O or Memory mapped registers of a PCI device.  Since this routine
* accesses only a single byte of data no address or data manipulation is
* required.
*
* RETURNS: byte from address.
*/
i2cPciInByte:
	lbzx 3,0,3;
	bclr 20,0;
	
   
/*************************************************************
* Copy a long long type data from souAddr to destAddr
*
* void sysLongLongMove (UINT32 destAddr, UINT32 souAddr)
*/


sysLongLongMove:

		lfd  f0, 0(r4)

		stfd f0, 0(r3)
		sync
        /* Return to caller */
        bclr    20,0
        
/********************************************************
* void sysFpSet(ULONG tmp)
*
* Open the FP function.
*/

sysFpSet:
	mfmsr r3
	ori r3, r3, 0x2000
	mtmsr r3
	sync
	
	bclr 20,0
	
	

/* Add these two function for PC97307, xdg, 11.29 */

/*******************************************************************************
*
* sysSioRead - this function reads a register from the UIO chip
*
* In order to read data from the desired Super IO register, the index register
* must be written to with the offset of the of the register to be read.  The 
* desired byte of data is then read from the data register.
*
* RETURNS: byte read from data register
*
* From a C point of view, the routine is defined as follows:

UINT8 sysSioRead
    ( 
    UINT8 * pSioIndexReg, 	/@ pointer to SIO index register base addr @/
    UINT8 sioRegOffset		/@ offset of register to read from @/
    )

*/

sysSioRead:
        stb     r4,0(r3)        /* write index register with register offset */
        eieio
        sync
        lbz     r3,1(r3)        /* retrieve specified reg offset contents */
        eieio
        sync
        bclr    20,0            /* return to caller */

/*******************************************************************************
*
* sysSioWrite - this function writes a register to the UIO chip
*
* In order to write data to the desired Super IO register, the index
* register must be written to with the offset of the of the register to be
* modified.  The desired byte of data can then be written via the data
* register.
*
* RETURNS: N/A
*
* From a C point of view, the routine is defined as follows:

void sysSioWrite
    ( 
    UINT8 * pSioIndexReg, 	/@ pointer to SIO index register base addr @/
    UINT8 sioRegOffset, 	/@ offset of register to write to @/
    UINT8 data			/@ 8-bit data to be written @/
    )

*/

sysSioWrite:
        stb     r4,0(r3)        /* write index register with register offset */
        eieio
        sync
        stb     r5,1(r3)        /* 1st write */
        eieio
        sync
        stb     r5,1(r3)        /* 2nd write */
        eieio
        sync
        bclr    20,0            /* return to caller */

/**********************************************************
 * function: load_runtime_reg
 *
 * input:  r3 - value of eumbbar
 *         r4 - register offset in embedded utility space
 *
 * output: r3 - register content
 **********************************************************/
load_runtime_reg:
	     
		  xor r5,r5,r5
          or  r5,r5,r3       /* save eumbbar */

	      lwbrx	r3,r4,r5
	      sync

 	      bclr 20, 0

/****************************************************************
 * function: store_runtime_reg
 *
 * input: r3 - value of eumbbar
 *        r4 - register offset in embedded utility space
 *        r5 - new value to be stored 
 *
 ****************************************************************/
store_runtime_reg:

		  xor r0,r0,r0

	      stwbrx r5,  r4, r3
	      sync

		  bclr   20,0
/**************************************************************************
*  get_eumbbar -- return EUMBBAR setting in R3
*/
         
get_eumbbar:      
		xor     r0,r0,r0
		addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
    	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
    	addi	r3,r6,MPC8240_CFG_EUMBBAR /* add EUMBBAR offset */
		addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
		ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
		stwbrx	r3,r0,r7		/* write address of EUMBBAR to CAR */
		sync	
		addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
		ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
		lwbrx	r3,r0,r4		/* read EUMBBAR */
		sync				/* ensure memory access is complete */		
		blr
get_kahlua_pcsrbar:

		blr

runled:
	addis    r4,0,0xFF00
/*	addis      r3,0,0xff00
    stw      r3,0x0(r4)*/
    addis     r5,0,0x0000
	ori       r5,r5,0x0000
    

alloop1:        
    addis      r3,0,0x0100
    stw      r3,0x0(r4) 
	addis	r6,0,0x10
	mtspr	CTR,r6	
	eieio
	sync
write1_loop1:
	eieio
	bc	16,0,write1_loop1	
	addis      r3,0,0x0300
    stw      r3,0x0(r4)
	addis	r6,0,0x10
	mtspr	CTR,r6	
	eieio
	sync
write_loop1:
	eieio
	bc	16,0,write_loop1	
	eieio
	sync
	
       addi     r5,r5,0x0001
	cmpwi      r5, 0x3
        bne        alloop1
        blr