📄 config.h
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* All definitions for these constants must be identical.
*/
#ifdef FLASH_BOOT
# define ROM_BASE_ADRS FLASH_BASE_ADRS /* base address of flash */
# define ROM_TEXT_ADRS FLASH_TEXT_ADRS
#else
# define ROM_BASE_ADRS 0xfff00000 /* base addr of socketed ROM */
# define ROM_TEXT_ADRS (ROM_BASE_ADRS + 0x100)
#endif /* FLASH_BOOT */
#define ROM_SIZE 0x00080000 /* 0.5 Meg ROM space */
/* Setup the sizes of the various PCI window spaces */
/*
* Size of the PReP PCI I/O space,
* up to 0x3f000000 bytes (1GB - 16MB ) are available for this space.
* Note: this size is used in setting up the page table entry for this
* PCI space, so setting this to a large value will tie up DRAM.
*/
#ifndef CHRP_ADRS_MAP
# define PCI_MSTR_IO_SIZE 0x00400000 /* 4MB window by default */
#endif
/*
* size of the PCI ISA memory space area. 4MB default, 16MB MAX
* DO NOT make the value of ISA_MSTR_MEM_SIZE greater than 16MB.
*/
#ifdef ISA_MEM_SPACE
# define ISA_MSTR_MEM_SIZE 0x00400000 /* 4MB window by default */
#endif
/*
* Size of the PCI nonprefetchable memory space ( this does not include
* the legacy ISA memory space, it is mapped in a different address space
* and is not configured by default. Refer to the define ISA_MEM_SPACE for
* more information regarding this space and information on how to set it up).
* Need at least 64MB if using PCI-PCI bridging.
*/
#define PCI_MSTR_MEMIO_SIZE 0x04000000 /* 64MB default */
/* #define PCI_MSTR_MEMIO_SIZE 0x08000000 */ /* modify by zoutl for test 2003-4-29 17:39 */
/*
* Size of the prefetchable PCI memory space,
* this determines the amount of PCI MEM space available for use
* by the PCI autoconfig routine.
*/
/* #define PCI_MSTR_MEM_SIZE 0x40000000 */ /* 1GB(Galnet used)+16MB default */
#define PCI_MSTR_MEM_SIZE 0x10000000 /* modify by zoutl for boot fast 2003-3-14 9:49 */
/*
* These defines are used to initialize the External Source
* Vector/Priority registers in the EPIC. The following can
* be defined: interrupt sensitivity, polarity and interrupt priority.
*
* Note: by default a 0 into the sense bit(22) will setup for level
* sensitive, and a 0 into the polarity bit(23) will setup for low
* polarity.
*
* At initialization all external interrupt sources are disabled.
*
* All currently unused interrupt sources are set to a priority of
* 0, which will not allow them to be enabled. If any one of these
* levels is to be used, the priority value must be changed here.
*/
#define INIT_SER_SRC0 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* not used */
#define INIT_SER_SRC1 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* not used */
#define INIT_SER_SRC2 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL3 ) /* debug interrupt */
#define INIT_SER_SRC3 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* Not used */
#define INIT_SER_SRC4 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* Not used */
#define INIT_SER_SRC5 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* Not used */
#define INIT_SER_SRC6 ( INT_MASK_BIT |\
EDGE_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* Not used */
#define INIT_SER_SRC7 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL13 ) /* PCI expansion INTA,
DEC2155X */
#define INIT_SER_SRC8 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL14 ) /* PCI expansion INTB,
primary ethernet */
#define INIT_SER_SRC9 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL13 ) /* PCI expansion INTC */
#define INIT_SER_SRC10 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL13 ) /* PCI expansion INTD */
#define INIT_SER_SRC11 ( INT_MASK_BIT |\
EDGE_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* not used */
#define INIT_SER_SRC12 ( INT_MASK_BIT |\
EDGE_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* not used */
#define INIT_SER_SRC13 ( INT_MASK_BIT |\
LEVEL_SENSE |\
HIGH_POLARITY |\
PRIORITY_LVL5 ) /* 16550 UART (COM1) */
#define INIT_SER_SRC14 ( INT_MASK_BIT |\
EDGE_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL4 ) /* abort switch */
#define INIT_SER_SRC15 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL0 ) /* Not used */
/* External interrupt sources */
#define INIT_EXT_SRC0 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL10 )
#define INIT_EXT_SRC1 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL13 ) /* i82559 PMCINTB*/
#define INIT_EXT_SRC2 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL10 )
#define INIT_EXT_SRC3 ( INT_MASK_BIT |\
LEVEL_SENSE |\
LOW_POLARITY |\
PRIORITY_LVL10 )
#define INIT_EXT_SRC4 ( INT_MASK_BIT |\
LEVEL_SENSE |\
HIGH_POLARITY |\
PRIORITY_LVL10 ) /* serial on pmc card */
/* Initial timer values */
#define INIT_TMR_SRC0 ( TIMER_INHIBIT |\
PRIORITY_LVL0 ) /* AUX Clock */
#define INIT_TMR_SRC1 ( TIMER_INHIBIT |\
PRIORITY_LVL0 ) /* off */
#define INIT_TMR_SRC2 ( TIMER_INHIBIT |\
PRIORITY_LVL0 ) /* off */
#define INIT_TMR_SRC3 ( TIMER_INHIBIT |\
PRIORITY_LVL0 ) /* off */
/* Initial DMA interrupt values */
#define INIT_DMA_SRC0 ( INT_MASK_BIT |\
PRIORITY_LVL0 ) /* off */
#define INIT_DMA_SRC1 ( INT_MASK_BIT |\
PRIORITY_LVL0 ) /* off */
/* Initial I2C interrupt value */
#define INIT_I2C_SRC ( INT_MASK_BIT |\
PRIORITY_LVL0 ) /* off */
/* Initial message unit interrupt value */
#define INIT_MSGUNIT_SRC ( INT_MASK_BIT |\
PRIORITY_LVL0 ) /* off */
#define INIT_DUART_SRC1 ( INT_MASK_BIT |\
PRIORITY_LVL5 ) /* serial on pmc card */
#define INIT_DUART_SRC2 ( INT_MASK_BIT |\
PRIORITY_LVL6 ) /* modified by zoutl:PRIORITY_LVL0--> PRIORITY_LVL6*/
/* BSP-specific includes */
#include "prpmc600.h"
/* serial parameters */
#undef NUM_TTY
#define NUM_TTY N_SIO_CHANNELS
#undef CONSOLE_TTY
#define CONSOLE_TTY 0 /*use pmc8240 own com*/
/*#undef INCLUDE_CACHE_SUPPORT
#undef USER_D_CACHE_ENABLE */ /* undef to leave disabled*/
/*#undef USER_B_CACHE_ENABLE */ /* undef to leave disabled*/
/*#undef USER_I_MMU_ENABLE */ /* undef to leave disabled*/
/*#undef USER_D_MMU_ENABLE */ /* undef to leave disabled*/
#define I82559_VENDOR_ID 0x8086
#define I82559ER_DEVICE_ID 0x1209
#define GT48004_ID 0x480411AB
#define PCI_MEMIO2LOCAL(x) (x)
#define LOCAL2PCI_MEMIO(x) (x)
/*use external pci arbiter*/
/*#define INCLUDE_PCI_EXTARBITER */
#if(0)/* changed by wanggeng from 1 to 0 20050802*/
#define INCLUDE_PCI9030
#define PCI9030_CFG_BASE 0x8000a000
#define PCI9030EXTFLASHMEM 0xa0000000
#define PCI9030EXTFLASHSIZE 0x001000000
#define PCI9030_ID 0x903010b5
#endif
/*
* The prpmc600 can access two Ethernet devices, one is the Intel
* 82559 chip on-board. The other is the DEC21143 on the carrier
* board. The I82559 is designated at the primary ethernet device
* by default, and the DEC21143 is the secondary device. This can
* be reversed by swapping the IDSEL values for PCI_IDSEL_PRI_LAN
* and PCI_IDSEL_SEC_LAN.
*/
#define PCI_IDSEL_PRI_LAN 16 /*82559ER PCI IDSEL*/
#define PCI_IDSEL_SEC_LAN 14 /*not use*/
/*
* This table describes the PCI IDSEL-to-MPIC interrupt routing. The default
* table supports the PrPMC600 mated to the PRPMCBASE-001 carrier board.
* If this BSP is adapted to a customer
* designed carrier board, this table must be modified to reflect the
* IDSEL-to-PCI interrupt routing implemented by the board designers. PCI
* Auto-Configuration uses this table to determine the proper value for the
* intLine field of the PCI header.
*/
#define W83C553_DEVNO 11
#define INTERRUPT_ROUTING_TABLE \
static UCHAR intLine [][4] = \
{ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 0 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 1 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 2 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 3 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 4 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 5 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 6 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 7 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 8 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 9 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 10 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 11 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 12 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 13 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 14 */ \
{ 0xff, 0xff, 0xff, 0xff }, /* device number 15 */ \
{ PCI_8139_INT_VEC, /* device number 16 I82559/I8139 on PrPMC600 */ \
0xff, \
0xff, \
0xff }, \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 17 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 18 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 19 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 20 */ \
{ PCI_8139_INT_VEC, /* device number 21 */ \
0xff, \
0xff, \
0xff }, /* device number 21 */ \
{ PCI_8139_INT_VEC, /* device number 22 */ \
0xff, \
0xff, \
0xff }, \
{ PCI_8139_INT_VEC, /* device number 23 */ \
0xff, \
0xff, \
0xff }, \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 24 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 25 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 26 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 27 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 28 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff }, /* device number 29 */ \
{ PCI_8139_INT_VEC, 0xff, 0xff, 0xff } /* device number 30 */ \
};
#define USER_APPL_INIT
#ifdef __cplusplus
}
#endif
#if defined(PRJ_BUILD)
# include "prjParams.h"
#endif
/***************** 以下宏定义由邹同亮添加 *****************/
#ifndef XPBCON_EPLD_REG_BASE
#define XPBCON_EPLD_REG_BASE 0xff000000
#define XPBCON_EPLD_REG0 (XPBCON_EPLD_REG_BASE + 0)
#define XPBCON_EPLD_REG1 (XPBCON_EPLD_REG_BASE + 1)
#define XPBCON_EPLD_REG2 (XPBCON_EPLD_REG_BASE + 2)
#define XPBCON_EPLD_REG3 (XPBCON_EPLD_REG_BASE + 3)
#define XPBCON_EPLD_REG4 (XPBCON_EPLD_REG_BASE + 4)
#define XPBCON_EPLD_REG5 (XPBCON_EPLD_REG_BASE + 5)
#define XPBCON_EPLD_REG6 (XPBCON_EPLD_REG_BASE + 6)
#define XPBCON_EPLD_REG7 (XPBCON_EPLD_REG_BASE + 7)
#endif
/*
#ifndef BOOT_DEBUG_MSG
#define BOOT_DEBUG_MSG
#endif
*/
/*
#ifndef BSP_TEST
#define BSP_TEST
#endif
*/
/***************** 邹同亮添加的宏定义到此为止 ***************/
#endif /* INCconfigh */
#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif
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