config.h

MPC8241:本程序是freescale的824*系列的BSP源程序

/* config.h - Motorola PowerPlus board configuration header */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01d,22jun00,rhk  Defined FLASH_BOOT (soldered ROM) as a default.
01c,05jun00,rhk  changed SM_OFF_BOARD to TRUE for default value.
01b,10may00,rhk  Added Drawbridge support.
01a,23feb00,rhk  created. (from ver 01o, mv2100 BSP)
*/

/*
DESCRIPTION
This file contains the configuration parameters for the
Motorola PowerPlus architecture

Notes:
1. The PRPMC600 is built around the Motorola Mpc8240 PowerPC
integrated processor with a PowerPC 603 core.  

2. The PRPMC600 defaults to the PowerPC Common Hardware
Reference Platform (CHRP) address map.  This address map
allows for a large PCI memory address space.
The BSP is designed to work by default with the CHRP address map,
if the PReP (PowerPC Reference Platform) address map is desired,
then undef CHRP_ADRS_MAP.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif

/* The following defines must precede configAll.h */

/* BSP version/revision identification */
#define INCLUDE_USER_APPL

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/0.1"		/* 0 for first revision */

/* PRIMARY INCLUDES */

#include "configAll.h"

/* defines */

#if (CPU == PPC603)
#define DEFAULT_BOOT_LINE \
	"rtl(0,0)host:vxWorks h=10.128.3.34 e=10.128.2.30 u=target pw=target"  /*DEFAULT_BOOT_LINE
	         															   is modified by mashuyu*/
/*#   define DEFAULT_BOOT_LINE \
	"er(0,0)host:vxWorks h=10.51.49.28 e=10.51.49.1 u=target pw=target"*/
/*#   define DEFAULT_BOOT_LINE \
	"tffs=0,(0,0)host:RFA/vxWorks h=10.51.49.28 e=10.51.49.1 u=target pw=target"*/	
#   define WRONG_CPU_MSG "A PPC603 VxWorks image cannot run on a PPC604!\n";
#endif	/* (CPU == PPC604) */

#define INCLUDE_TFFS
#define INCLUDE_SHOW_ROUTINES /* optional */
#define INCLUDE_DOSFS
/*#define INCLUDE_WDB_TSFS*/
/*
 * The following cPCI address accesses the beginning of system
 * (cPCI master) DRAM.  This should be set to:
 *     0x80000000 if the cPCI master is an MCP750;
 *     0x00000000 if the cPCI master is a CPV5x00.
 */
/*#define PCI_AUTO_DEBUG*/
#define CPCI_MSTR_MEM_BUS       0x80000000

/* define, if SHOW routines are to be included */

/* #undef INCLUDE_SHOW_ROUTINES */ /* mask by zoutl 2002-4-22 17:40 */

/*
 * Default board configurations
 *
 * If a supported feature is desired,
 *         change to: #define
 * If a feature is not desired or not supported
 *         change to: #undef
 *
 * NOTE: Not all functionality is supported on all boards
 */
#ifndef PRPMC600
#define PRPMC600
#endif


#ifdef PRPMC600
	#undef	INCLUDE_CACHE_L2	/* [NOT AVAILABLE] */
	#undef	INCLUDE_SCSI		/* [NOT AVAILABLE] */
	#define	INCLUDE_AUXCLK		/* Auxiliary clock support */
	#undef	INCLUDE_ECC		/* Mpc8240 ECC */
	#define	INCLUDE_HW_FP		/* Mpc8240 1.0 doesn't have FP */
	#undef  FLASH_BOOT		/* select ROM base, default: soldered */
							/* flash_boot means boot from soldered flash */
	#define INCLUDE_END             /* Enhanced Network Driver */
	/* #define INCLUDE_FEI_END */     /* Fei 82559 Ethernet Controller */ /*modified by mashuyu*/
	#define INCLUDE_RTL_CP_END
	
#endif


/* Address mapping select, CHRP is enabled by default, #undef selects PReP */

#define	CHRP_ADRS_MAP

/* 
 * The MCP8240 processor defines a 16MB block of PCI space for access
 * to ISA memory space.  This is located at address 0xfd000000 for CHRP
 * mode addressing and at 0xc0000000 for PReP mode.  This space is designed
 * for legacy ISA devices and is mapped into zero-based PCI memory space to
 * allow for 16-bit and 24-bit ISA addressing.  By default this address
 * space is not used.  If it is required, then define ISA_MEM_SPACE. 
 */

#define ISA_MEM_SPACE


/* MMU and Cache options */

#define	INCLUDE_MMU_BASIC       /* bundled mmu support */
/*#undef	INCLUDE_MMU_BASIC*/
#undef	USER_D_CACHE_MODE
#define	USER_D_CACHE_MODE       (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)

/* timestamp option not included by default;  #define to include it */

#undef  INCLUDE_TIMESTAMP

/* De-select unused (default) network drivers selected in configAll.h */

#undef  INCLUDE_EX              /* include Excelan Ethernet interface */
#undef  INCLUDE_ENP             /* include CMC Ethernet interface*/

/* PCI bus numbers for secondary and subordinate buses */

#define PCI_SECONDARY_BUS       1
#define PCI_SUBORD_BUS          1

#undef	PCI_MAX_BUS
#define PCI_MAX_BUS             2       /* Max. number of PCI buses in system */

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.
 */

#ifndef  INCLUDE_AUXCLK
#    undef INCLUDE_SPY
#else
#    define INCLUDE_SPY
#endif /* INCLUDE_AUXCLK */

/* Shared-memory Backplane Network parameters */

/*
 * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane
 * driver and the auto address setup which are defined in configAll.h.
 * To exclude them, uncomment the following lines:
 *
 * #undef INCLUDE_SM_NET
 * #undef INCLUDE_SM_SEQ_ADDR
 */

#ifndef INCLUDE_DEC2155X
#   undef INCLUDE_SM_NET        /* requires 2155X support */
#   undef INCLUDE_SM_SEQ_ADDR   /* requires 2155X support */
#endif

#if defined(INCLUDE_SM_NET)

#   define STANDALONE_NET
#   define INCLUDE_NET_SHOW
#   define INCLUDE_BSD

    /*
     * Finding the shared memory anchor:
     *
     * There are four ways to communicate the location of the anchor to the
     * initialization code:
     *
     * 1) If "sm=xxxxxxxx" is specified as a boot parameter, then "xxxxxxxx"
     *    is used as the address of the anchor as view by the local CPU.
     *
     * 2) If case (1) above is not satisfied and the local CPU is the shared
     *    memory master (processor == 0), then if SM_OFF_BOARD is FALSE,
     *    the address LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET is used as the
     *    local address of the anchor.
     *
     * 3) If case (1) above is not satisfied and the local CPU is the shared
     *    memory master and SM_OFF_BOARD is defined as TRUE, then the shared
     *    memory anchor must be in system memory at CPCI_MSTR_MEM_BUS +
     *    SM_ANCHOR_OFFSET.
     *
     * 4) If case (1) above is not satisfied and the local CPU is not the
     *    shared memory master (processor != 0), the local CPU searches for
     *    the location of the shared memory anchor. Devices on the compactPCI
     *    bus (defined by SYS_SM_CPCI_BUS_NUMBER) are queried through the first
     *    memory BAR.  Memory at offset SM_ANCHOR_OFFSET is examined to
     *    determine if the anchor is there.
     *
     *    If SYS_SM_ANCHOR_POLL_LIST is defined then only those
     *    devices whose device/vendorID and subsystem device/vendorID
     *    are defined in this list are queried.  If SYS_SM_ANCHOR_POLL_LIST
     *    is NOT defined then ALL devices found on SYS_SM_CPCI_BUS_NUMBER
     *    are queried.
     *
     *    In addition if SYS_SM_SYSTEM_MEM_POLL is defined, the
     *    system memory (at compact PCI address CPCI_MSTR_MEM_BUS +
     *    SM_ANCHOR_OFFSET) is also queried for a possible location for
     *    the anchor.  If SYS_SM_SYSTEM_MEM_POLL is not defined, then
     *    system memory is not polled.  This option would typically be
     *    used if the anchor resided on an MCP750 and the initialization
     *    code was running on an MCPN750.
     */

#   define SYS_SM_SYSTEM_MEM_POLL

    /*
     * When shared memory anchor polling is enabled, the following defines the
     * PCI bus number on which to poll devices for the shared memory anchor.
     */

#   define SYS_SM_CPCI_BUS_NUMBER    1

    /*
     * SM_OFF_BOARD is used by processor 0 to determine the proper address for
     * the shared memory anchor. It is not used by other processors.
     */

#   define SM_OFF_BOARD TRUE   /* Memory pool is off-board */

#   define SM_MEM_OFFSET        0x4d00  /* offset to start of shared memory */

   /*
    * If the anchor is offboard (SM_OFF_BOARD == TRUE), then place the
    * anchor SM_ANCHOR_OFFSET at 0x4100 if the actual anchor is on an
    * MCP750 or MCPN750, or place it at 0x1100 if the actual anchor is
    * on a CPV5x00.
    */

#   undef  SM_ANCHOR_OFFSET
#   define SM_ANCHOR_OFFSET 0x4100  /* use 0x1100 for CPV5x00 master */

#   undef SM_ANCHOR_ADRS
#   define SM_ANCHOR_ADRS       (sysSmAnchorAdrs())

#   define LOCAL_SM_ANCHOR_ADRS (LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET)

    /*
     * The following defines are only used by the master.
     * The slave only uses the "Anchor" address.
     *
     * The definition of SM_MEM_ADRS is structured to allow a Monarch PrPMC to
     * create a shared memory pool in system memory (on the MCP750 or CPV5x00)
     * without knowing where the Monarch's PCI Auto-Configuration placed the
     * upstream window in the local PCI address space.
     */

#   define SM_MEM_ADRS          (SM_ANCHOR_ADRS - SM_ANCHOR_OFFSET + \
                                 SM_MEM_OFFSET)
#   define SM_MEM_SIZE          0x00010000
#   define SM_OBJ_MEM_ADRS      (SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */
#   define SM_OBJ_MEM_SIZE      0x00010000

    /*
     * Because operating mode is determined at runtime, shared memory related
     * parameters cannot be set at complile-time. The functions below are used
     * to determine the proper shared memory parameters are runtime.
     */

#   ifndef _ASMLANGUAGE
        IMPORT  char * sysSmAnchorAdrs();
	IMPORT  int    smIntArg1;
        int     sysSmArg2Compute (void);
#   endif

    /*
     * The following defines control the in-bound interrupt method.
     *
     * SM_HOST_INT_TYPE is used to
     * control the method used by cPCI devices when interrupting via the 21554.
     * Supported values are SM_INT_MAILBOX_1 (using a 21554 "doorbell" bit) or
     * SM_INT_NONE (polling).
     */

#   define  SM_HOST_INT_TYPE  SM_INT_MAILBOX_1	/* "doorbell" register int. */	

    /*
     * SM_INT_ARG1 is calculated in sysSmParamsCompute(), "sysLib.c"
     * SM_INT_ARG2 is dynamically calculated in sysSmArg2Compute(), "sysLib.c"
     */

#   define SM_INT_TYPE  SM_INT_MAILBOX_1  /* "doorbell" register int. */
#   define SM_INT_ARG1  (smIntArg1)
#   define SM_INT_ARG2  (sysSmArg2Compute())
#   define SM_INT_ARG3  (1 << (DEC2155X_SM_DOORBELL_BIT % 8))

    /*
     * The array fragment below lists the devices which could contain the shared
     * memory anchor. The boards are listed by subsystem vendor ID and
     * subsystem ID.  To add new boards, simply add them to the list.
     */

#   define SYS_SM_ANCHOR_POLL_LIST \
        SYS_MOT_SM_ANCHOR_POLL_LIST

    /*
     * The array fragment below lists devices which participate in shared memory
     * backplane networking. The boards are listed by subsystem vendor ID and
     * subsystem ID. To add new boards, simply add them to the list.
     */

#   define SYS_SM_DEVICE_LIST \
        SYS_MOT_SM_DEVICE_LIST

#endif /* defined(INCLUDE_SM_NET) */

/*
 * Note: The PrPMC600 requires a modified software Test and Set algorithm.
 * SM_TAS_TYPE is set to SM_TAS_HARD despite the lack of a hardware TAS
 * mechanism to force the use of a BSP-specific software TAS algorithm. The
 * modified algorithm is required to work around a problem encountered with
 * PCI-to-PCI bridges.
 */

#undef SM_TAS_TYPE
#define SM_TAS_TYPE     SM_TAS_HARD

/*
 * The following must be a value between 0 and 15.  It represents the
 * bit number of the primary doorbell register used to interrupt the
 * MCP750 for shared memory bus interrupts.
 */

#define DEC2155X_SM_DOORBELL_BIT 0

/*
 * Local Memory definitions
 *
 * By default, the available DRAM memory is sized at bootup (LOCAL_MEM_AUTOSIZE
 * is defined).  If auto-sizing is not selected, make certain that
 * LOCAL_MEM_SIZE is set to the actual amount of memory on the board.
 * By default, it is set to the minimum memory configuration: 16 MB.
 * Failure to do so can cause unpredictable system behavior!
 */

#undef	LOCAL_MEM_AUTOSIZE			/* undef for fixed size */
#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */
#define LOCAL_MEM_SIZE   	0x02000000  /* Default: Min memory: 32MB */
/* #define LOCAL_MEM_SIZE   	0x08000000 */ /* memory: 128MB */


#define RAM_HIGH_ADRS		0x00800000 	/* RAM address for ROM boot */
#define RAM_LOW_ADRS		0x00100000	/* RAM address for kernel */

/* user reserved memory, see sysMemTop() */

#define USER_RESERVED_MEM	(0)	/* number of reserved bytes */

#define	FLASH_TEXT_ADRS	(FLASH_BASE_ADRS + 0x100) /* 0xff000100 */

/*
 * The constants ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS 
 * are defined in config.h, Makefile.