📄 rtlcpp.c
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rtl81x9CsrWriteByte(pDrvCtrl, RTL_REGS_CONFIG3, ByteIn8139, RTL_WIN_0);
pciConfigInWord(0, 21, 0, PCI_CFG_COMMAND, &usCommand);
pciConfigOutWord(0, 21, 0, PCI_CFG_COMMAND, usCommand|0x0210);
pciConfigOutByte(0, 21, 0, PCI_CFG_CACHE_LINE_SIZE, 0x08);
/* add by zoutl for test 2003-4-6 19:22 */
/***************kongfq 20005.8.15**************************/
pDrvCtrl->ivec = PCI_8139_INT_VEC;
pDrvCtrl->ilevel = PCI_8139_INT_VEC;
/* logMsg("RTL81x9 start\n",1 , 2, 3, 4, 5, 6);
logMsg("int number 0X:%x\n the level is 0x%x",pDrvCtrl->ivec,pDrvCtrl->ilevel,3,4,5,6);*/
pDrvCtrl->txBlocked = FALSE;
pDrvCtrl->proc_rx=0;
SYS_INT_CONNECT (pDrvCtrl, rtl81x9Int, (int)pDrvCtrl, &result);
if (result == ERROR)
return ERROR;
SYS_INT_ENABLE (pDrvCtrl);
/* Init the RX buffer pointer register. */
/*first enable tx rx for descriptor write */
rtl81x9CsrWriteByte(pDrvCtrl, RTL_REGS_CHIP_CMD, RTL_CMD_RX_ENB + RTL_CMD_TX_ENB, RTL_WIN_0);
/* diff= (UINT32) pDrvCtrl->ptrRxBufSpace-(((UINT32)pDrvCtrl->ptrRxBufSpace >> 8)<< 8);
diff=256-diff;
pDrvCtrl->ptrRxBufSpace+=diff;
*/
/* modify by zoutl for test 2003-4-6 19:56 */
rtl81x9CsrWriteWord(pDrvCtrl, RTL_REGS_CPCR,(USHORT) CPRX|CPTX|CPMULRX, RTL_WIN_0);/*enable rx tx use c+ mode*/
/*
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_RDSAR_0, (ULONG) pDrvCtrl->ptrRxBufSpace, RTL_WIN_0);
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_RDSAR_1, (ULONG) 0, RTL_WIN_0);
*/
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_RDSAR_0, (ULONG) pDrvCtrl->ptrRxBufSpace, RTL_WIN_0);
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_RDSAR_1, (ULONG) 0, RTL_WIN_0);
DRV_LOG (DRV_DEBUG_START, "rxbuffer start- %x: \n", rtl81x9CsrReadLong(pDrvCtrl, RTL_REGS_RDSAR_0, RTL_WIN_0), 2, 3, 4, 5, 6);
DRV_LOG (DRV_DEBUG_START, "rxbuffer start- %x: \n", (ULONG) pDrvCtrl->ptrRxBufSpace , 2, 3, 4, 5, 6);
/* Init the TX buffer pointer register. */
/*diff= (UINT32) pDrvCtrl->ptrTxBufSpace-(((UINT32)pDrvCtrl->ptrTxBufSpace >> 8)<< 8);
diff=256-diff;
pDrvCtrl->ptrTxBufSpace+=diff;
*/
/* modify by zoutl 2003-4-5 20:19 */
/*
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_TX_START_NOR_0, (ULONG) pDrvCtrl->ptrTxBufSpace, RTL_WIN_0);
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_TX_START_NOR_1, (ULONG) 0, RTL_WIN_0);
*/
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_TX_START_HIGH_0, (ULONG) pDrvCtrl->ptrTxBufSpace, RTL_WIN_0);
rtl81x9CsrWriteLong(pDrvCtrl, RTL_REGS_TX_START_HIGH_1, (ULONG) 0, RTL_WIN_0);
/* modify by zoutl for test 2003-4-5 20:19 */
DRV_LOG (DRV_DEBUG_START, "txbuffer start- %x read back=%x: \n",(ULONG) pDrvCtrl->ptrTxBufSpace , rtl81x9CsrReadLong(pDrvCtrl, RTL_REGS_TX_START_NOR_0, RTL_WIN_0), 3, 4, 5, 6);
/* Enable cplus Tx and RX */
/*rtl81x9CsrWriteWord(pDrvCtrl, RTL_REGS_CPCR,(USHORT) CPRX|CPTX, RTL_WIN_0);*//*enable rx tx use c+ mode*/
/*
* Set the initial TX and RX configuration.
* Set the buffer size and set the wrap register
*/
rtl81x9CsrWriteByte(pDrvCtrl, RTL_REGS_ETTHR, 0x00, RTL_WIN_0); /* add by zoutl for test 2003-4-3 16:57 */
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_TX_CONFIG, RTL_TXCFG_CONFIG, RTL_WIN_0);
/* DRV_LOG (DRV_DEBUG_ALL, "rtl81x9-TXCFG - %x: \n",RTL_TXCFG_CONFIG , 2, 3, 4, 5, 6);*/
/********KONGFQ2005.8.29*********/
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_CONFIG, RTL_RXCFG_CONFIG|ALL_ETH_FRAME_ENABLE, RTL_WIN_0);
/* rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_CONFIG, RTL_RXCFG_CONFIG|ALL_ETH_FRAME_ENABLE, RTL_WIN_0); */
rxcfg = rtl81x9CsrReadLong(pDrvCtrl, RTL_REGS_RX_CONFIG, RTL_WIN_0);
/* Set the Early Threshold bits depending on flags read */ /*vicadd*/
/* from initialisation string */
/*rxcfg |= ((pDrvCtrl->flags >> 16) << 24);*/
/* Set the individual bit to receive frames for this host only. */
rxcfg |= RTL_RXCG_APM;
/* If we want promiscuous mode, set the allframes bit. */
if (pDrvCtrl->ib->rtlIBMode == 0x8000)
{
rxcfg |= RTL_RXCG_AAP;
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_CONFIG, rxcfg, RTL_WIN_0);
}
else
{
rxcfg &= ~RTL_RXCG_AAP;
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_CONFIG, rxcfg, RTL_WIN_0);
}
/*
* Set capture broadcast bit to capture broadcast frames.
*/
rxcfg |= RTL_RXCG_AB;
DRV_LOG (DRV_DEBUG_START, "rtl81x9-RCR - %x: \n", rxcfg, 2, 3, 4, 5, 6);
pDrvCtrl-> reg_rcr =rxcfg;/* save it */
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_CONFIG, rxcfg, RTL_WIN_0);
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_RXMSR , RTL81x9_BUFSIZE, RTL_WIN_0); /*limit the max receive size 1536*/
/* We now need to update the Multicast Registers */
/* These values need to be finalised and written */
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_MAR0, 0xffff, RTL_WIN_0);
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_MAR0 + 4, 0xffff, RTL_WIN_0);
/* Enable Controller Interrupts */
/*vicadd*/
if(pDrvCtrl->flags & RTL_FLG_POLLING)
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_MASK, 0, NONE);
else
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_MASK, RTL_VALID_INTERRUPTS, NONE);
/* DRV_LOG (DRV_DEBUG_ALL, "rtl81x9-IMR - %x: \n",RTL_VALID_INTERRUPTS , 2, 3, 4, 5, 6);*/
/* Start RX/TX process. */
rtl81x9CsrWriteLong (pDrvCtrl, RTL_REGS_RX_MISSED, 0, RTL_WIN_0);
/* Enable Tx and RX */
/* rtl81x9CsrWriteByte(pDrvCtrl, RTL_REGS_CHIP_CMD, RTL_CMD_RX_ENB + RTL_CMD_TX_ENB, RTL_WIN_0);*/
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTMITIR , 0x5555, RTL_WIN_0);
taskDelay(10);
/*testvalue= rtl81x9CsrReadWord (pDrvCtrl, RTL_REGS_CPCR, RTL_WIN_0);
printf("CPCR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadByte (pDrvCtrl, RTL_REGS_CHIP_CMD, RTL_WIN_0);
printf("CR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_RX_CONFIG, RTL_WIN_0);
printf("RCR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_CONFIG, RTL_WIN_0);
printf("TCR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadWord (pDrvCtrl, RTL_REGS_INTR_MASK, RTL_WIN_0);
printf("IMR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadWord (pDrvCtrl, RTL_REGS_INTR_STATUS, RTL_WIN_0);
printf("ISR is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_ADDR0, RTL_WIN_0);
printf("TSAD0 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_ADDR1, RTL_WIN_0);
printf("TSAD1 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_ADDR2, RTL_WIN_0);
printf("TSAD2 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_ADDR3, RTL_WIN_0);
printf("TSAD3 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_STATUS0, RTL_WIN_0);
printf("TSD0 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_TX_STATUS1, RTL_WIN_0);
printf("TSD1 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong(pDrvCtrl, RTL_REGS_RDSAR_0, RTL_WIN_0);
printf("RDSAR0 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadLong(pDrvCtrl, RTL_REGS_RDSAR_1, RTL_WIN_0);
printf("RDSAR1 is 0x%x\n",testvalue);
testvalue= rtl81x9CsrReadByte(pDrvCtrl, RTL_REGS_ETTHR, RTL_WIN_0);
printf("ETTHR is 0x%x\n",testvalue);*/
DRV_LOG (DRV_DEBUG_START, "RTL81x9 start out\n",1 , 2, 3, 4, 5, 6);
return (OK);
}
/*******************************************************************************
*
* rtl81x9Int - handle controller interrupt
*
* This routine is called at interrupt level in response to an interrupt from
* the controller.
*
* RETURNS: N/A.
*/
#ifdef DRV_TEST_8139
unsigned int g_8139RecvIntNum; /* add by zoutl for test 2003-4-10 8:58 */
#endif
LOCAL void rtl81x9Int
(
RTL81X9END_DEVICE *pDrvCtrl
)
{
u_short stat;
int int_count=0;
/* Disable controller interrupts. */
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_MASK, 0x00, NONE);
/* logMsg("rtl81x9Int!!!\n", 0,0,0,0,0,0); */ /************kongfq2005.8.16******************/
for (;;)
{
/* Read the interrupt status register */
stat = rtl81x9CsrReadWord (pDrvCtrl, RTL_REGS_INTR_STATUS, NONE);
/* DRV_LOG (DRV_DEBUG_INT, "ISR %x ", stat,0,0,0,0,0); */
/* clear interrupts, */
if (stat)
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_STATUS, stat, NONE);
/* Check if a valid Interrupt has been set */
if ((stat & RTL_VALID_INTERRUPTS) == 0)
break;
/* mask by zoutl for test 2003-4-7 21:37 */
#if 0
if (stat & RTL_IPT_PCI_ERR)
{
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_PCI_ERR - Reset and Re initialise\n", 0,0,0,0,0,0);
rtl81x9Reset (pDrvCtrl);
rtl81x9Restart (pDrvCtrl);
}
#endif
if (stat & RTL_IPT_PCS_TIMEOUT)
{
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_PCS_TIMEOUT\n", 0, 0, 0, 0, 0, 0);
}
if (stat & RTL_IPT_CABLE_LEN_CHG)
{
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_CABLE_LEN_CHG\n", 0, 0, 0, 0, 0, 0);
}
if (stat & RTL_IPT_RX_FIFO_OVER)
{
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_RX_FIFO_OVER\n", 0, 0, 0, 0, 0, 0);
rtl81x9CsrWriteByte(pDrvCtrl, RTL_REGS_CHIP_CMD, RTL_CMD_RX_ENB + RTL_CMD_TX_ENB, RTL_WIN_0); /* add by zou 2003/3/12 */
}
if (stat & RTL_IPT_RX_UNDERUN)
{
DRV_LOG (DRV_DEBUG_ERR, "RTL_IPT_RX_UNDERUN\n", 0, 0, 0, 0, 0, 0);
/* rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_RDSAR_1 , RTL_WIN_0); */ /* mask by zoutl 2003-4-7 16:40 */
/*rtl81x9Reset (pDrvCtrl);*/
/*vicadd*/
/* rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_STATUS, RTL_IPT_RX_OK|RTL_IPT_RX_OVERFLOW|RTL_IPT_RX_FIFO_OVER, NONE);*/
/* rxcfg=rtl81x9CsrReadLong (pDrvCtrl, RTL_REGS_RX_CONFIG, RTL_WIN_0);
DRV_LOG (DRV_DEBUG_ALL, "rtl81x9-RCR - %x: \n", rxcfg, 2, 3, 4, 5, 6);
*/
}
if (stat & RTL_IPT_RX_OVERFLOW)
{
if(pDrvCtrl->proc_rx==0)
{
pDrvCtrl->proc_rx=1;
if (netJobAdd ((FUNCPTR)rtl81x9HandleRecvInt, (int) pDrvCtrl,
0, 0, 0, 0) != OK)
DRV_LOG (DRV_DEBUG_INT, "xl: netJobAdd (rtl81x9HandleRecvInt) failed\n", 0, 0, 0, 0, 0, 0);
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_RX_OVERFLOW\n", 0, 0, 0, 0, 0, 0);
}
}
if (stat & RTL_IPT_TX_ERR)
{
if(pDrvCtrl->txBlocked == TRUE)
{
netJobAdd ((FUNCPTR) muxTxRestart, (int) &pDrvCtrl->end, 0, 0, 0, 0);
END_TX_SEM_TAKE (&pDrvCtrl->end, WAIT_FOREVER);
pDrvCtrl->txBlocked = FALSE;
END_TX_SEM_GIVE (&pDrvCtrl->end);
}
/* mask by zoutl 2003-4-7 16:41 */
/*
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_TX_ERR\n", 0, 0, 0, 0, 0, 0);
rtl81x9HandleTxInt (pDrvCtrl);
*/
}
if (stat & RTL_IPT_RX_ERR)
{
#ifdef DRV_TEST_8139
if(pDrvCtrl->unit == g_ucTestNetUnit)
{
g_8139RecvIntNum++;
}
#endif
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_RX_ERR\n", 0, 0, 0, 0, 0, 0);
if (netJobAdd ((FUNCPTR)rtl81x9HandleRecvInt, (int) pDrvCtrl,
0, 0, 0, 0) != OK)
DRV_LOG (DRV_DEBUG_INT, "xl: netJobAdd (rtl81x9HandleRecvInt) failed\n", 0, 0, 0, 0, 0, 0);
}
/* Check for transmit Interrupt */
if (stat & RTL_IPT_TX_OK)
{
#ifdef DRV_TEST_8139
if(pDrvCtrl->unit == g_ucTestNetUnit)
{
g_8139RecvIntNum++;
}
#endif
if(pDrvCtrl->txBlocked == TRUE)
{
netJobAdd ((FUNCPTR) muxTxRestart, (int) &pDrvCtrl->end, 0, 0, 0, 0);
END_TX_SEM_TAKE (&pDrvCtrl->end, WAIT_FOREVER);
pDrvCtrl->txBlocked = FALSE;
END_TX_SEM_GIVE (&pDrvCtrl->end);
}
/* mask by zoutl 2003-4-7 16:41 */
/*
DRV_LOG (DRV_DEBUG_INT, "RTL_IPT_TX_OK\n", 0, 0, 0, 0, 0, 0);
rtl81x9HandleTxInt (pDrvCtrl);
*/
}
if (stat & RTL_IPT_RX_OK)
{
if(pDrvCtrl->proc_rx==0)
{
pDrvCtrl->proc_rx=1;
if (netJobAdd ((FUNCPTR)rtl81x9HandleRecvInt, (int) pDrvCtrl,
0, 0, 0, 0) != OK)
DRV_LOG (DRV_DEBUG_INT, "xl: netJobAdd (rtl81x9HandleRecvInt) failed\n", 0, 0, 0, 0, 0, 0);
}
}
if(int_count++>5) break;
}
rtl81x9CsrWriteWord (pDrvCtrl, RTL_REGS_INTR_MASK, RTL_VALID_INTERRUPTS, NONE);
}
/*******************************************************************************
*
* rtl81x9HandleTxInt - task level interrupt service for tx packets
*
* This routine is called by the interrupt service routine to do any
* message transmission processing.
*
* RETURNS: N/A.
*/
/* add by zoutl for test 2003-3-25 16:47 */
#ifdef DRV_TEST_8139
unsigned long g_GetClusterNum =0;
unsigned long g_FreeClusterNum =0;
#endif
/* add by zoutl for test 2003-3-25 16:47 */
#if 0
LOCAL void rtl81x9HandleTxInt
(
RTL81X9END_DEVICE *pDrvCtrl
)
{
int oldLevel;
descript* pTmd;
UINT32 tempcmd_leng;
static BOOL first;
first = TRUE;
DRV_LOG (DRV_DEBUG_TX, "TX int index=%x indexc=%x\n",pDrvCtrl->tmdIndex, pDrvCtrl->tmdIndexC, 0, 0, 0, 0);/* added by mashuyu */
if((pDrvCtrl->tmdIndexC == pDrvCtrl->tmdIndex)
&& (pDrvCtrl->txBlocked ))
{
(void) netJobAdd ((FUNCPTR) muxTxRestart, (int) &pDrvCtrl->end, 0, 0, 0, 0);
pDrvCtrl->txBlocked = FALSE;
}
while (pDrvCtrl->tmdIndexC != pDrvCtrl->tmdIndex)
{
pTmd = (descript*)( pDrvCtrl->ptrTxBufSpace + 16*pDrvCtrl->tmdIndexC);
/* RTL_CACHE_INVALIDATE (pTmd, 16); */ /* add by zoutl 2003-3-17 16:02 */
DRV_LOG (DRV_DEBUG_TX, "pTmd->cmd=%x \n", pTmd->cmd_leng, 0, 0, 0, 0, 0);/*added by mashuyu */
/* if (SHMEM_RD (&pTmd->cmd_leng) & 0x80000000)*/
/* cacheFlush(DATA_CACHE, pTmd, 16);*/ /* add by zoutl 2003-3-19 11:56 */
tempcmd_leng = PCI_SWAP (pTmd->cmd_leng);/* added by mashuyu */
/* if ( ((pTmd->cmd_leng) & 0x80000000)!=0) */
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