pciautoconfiglib.c

MPC8241:本程序是freescale的824*系列的BSP源程序

    {

    /@ 32-bit Prefetchable Memory Space @/

    sysParams.pciMem32 = PCI_MEM_ADRS;
    sysParams.pciMem32Size = PCI_MEM_SIZE;

    /@ 32-bit Non-prefetchable Memory Space @/

    sysParams.pciMemIo32 = PCI_MEM_ADRS;
    sysParams.pciMemIo32Size = PCI_MEM_SIZE;

    /@ 16-bit ISA I/O Space @/

    sysParams.pciIo16 = PCI_ISA_IO_ADRS;
    sysParams.pciIo16Size = PCI_ISA_IO_SIZE;

    /@ 32-bit PCI I/O Space @/

    sysParams.pciIo32 = PCI_IO_ADRS;
    sysParams.pciIo32Size = PCI_IO_SIZE;

    /@ Configuration space parameters @/

    sysParams.maxBus = 0;
    sysParams.cacheSize = ( _CACHE_ALIGN_SIZE / 4 );
    sysParams.maxLatency = PCI_LAT_TIMER;

    /@
     * Interrupt routing strategy
     * across PCI-to-PCI Bridges
     @/

    sysParams.autoIntRouting = TRUE;

    /@ Device inclusion and interrupt routing routines @/

    sysParams.includeRtn = sysPciAutoconfigInclude;
    sysParams.intAssignRtn = sysPciAutoconfigIntrAssign;

    /@
     * PCI-to-PCI Bridge Pre-
     * and Post-enumeration init
     * routines
     @/

    sysParams.bridgePreConfigInit =
	sysPciAutoconfigPreEnumBridgeInit;
    sysParams.bridgePostConfigInit =
	sysPciAutoconfigPostEnumBridgeInit;

    /@
     * Perform any needed PCI Host Bridge
     * Initialization that needs to be done
     * before pciAutoConfig is invoked here 
     * utilizing the information in the 
     * newly-populated sysParams structure. 
     @/

    pciAutoConfig (&sysParams);

    /@
     * Perform any needed post-enumeration
     * PCI Host Bridge Initialization here
     * utilizing the information in the 
     * sysParams structure that has been 
     * updated as a result of the scan 
     * and configuration passes. 
     @/

    }

    /@
     * Local BSP-Specific routines
     * supplied by BSP Developer
     @/

STATUS sysPciAutoconfigInclude
    (
    PCI_SYSTEM * pSys,			/@ PCI_SYSTEM structure pointer @/
    PCI_LOC * pLoc,			/@ pointer to function in question @/
    UINT devVend			/@ deviceID/vendorID of device @/
    )
    {
    return OK; /@ Autoconfigure all devices @/
    }

UCHAR sysPciAutoconfigIntrAssign
    (
    PCI_SYSTEM * pSys,			/@ PCI_SYSTEM structure pointer @/
    PCI_LOC * pLoc,			/@ pointer to function in question @/
    UCHAR pin				/@ contents of PCI int pin register @/
    )
    {
    return (UCHAR)0xff;
    }

void sysPciAutoconfigPreEnumBridgeInit
    (
    PCI_SYSTEM * pSys,			/@ PCI_SYSTEM structure pointer @/
    PCI_LOC * pLoc,			/@ pointer to function in question @/
    UINT devVend			/@ deviceID/vendorID of device @/
    )
    {
    return;
    }

void sysPciAutoconfigPostEnumBridgeInit
    (
    PCI_SYSTEM * pSys,			/@ PCI_SYSTEM structure pointer @/
    PCI_LOC * pLoc,			/@ pointer to function in question @/
    UINT devVend			/@ deviceID/vendorID of device @/
    )
    {
    return;
    }

.CE

CONFIGURATION SPACE PARAMETERS

The cache line size register specifies the cacheline size in longwords. 
This register is required when a device can generate a memory write and
Invalidate bus cycle, or when a device provides cacheable memory to the system. 

Note that in the above example, the macro _CACHE_ALIGN_SIZE is utilized. This
macro is implemented for all supported architectures and is located in the
<architecture>.h file in .../target/h/arch/<architecture>. The value of the
macro indicates the cache line size in bytes for the particular architecture.
For example, the PowerPC architecture defines this macro to be 32, while
the ARM 810 defines it to be 16. The PCI cache line size field and
the cacheSize element of the PCI_SYSTEM structure expect to see this quantity
in longwords, so the byte value must be divided by 4. 

LIMITATIONS

The current version of the autoconfig facility does not support 64-bit
prefetchable memory behind PCI-to-PCI bridges, but it does support
32-bit prefetchable memory.

The autoconfig code also depends upon the BSP Developer specifying resource
pools that do not conflict with any resources that are being used by 
statically configured devices.

INCLUDE FILES:

pciAutoConfigLib.h

SEE ALSO: 

.I "PCI Local Bus Specification, Revision 2.1, June 1, 1996"
.I "PCI Local Bus PCI to PCI Bridge Architecture Specification, Revision 1.0,
April 5, 1994"

INTERNAL: SIMPLE TEXT-BASED DEBUG SUPPORT

Note that the macro PCI_AUTO_DEBUG may be defined, and the macro
PCI_AUTO_DEBUG_MSG utilized. PCI_AUTO_DEBUG_MSG is identical to a function 
call to logMsg() in function in that it calls _func_logMsg() with the 
string and six parameters passed to it. The macro also invokes taskDelay 
to allow the debug string to be sent with minimal interruption.

Also note that the macro PCI_AUTO_DEBUG initializes a global variable 
pciAutoDebug to a non-zero value. Display of debug messages may be turned
on and off during runtime by manipulating this variable. If the variable is
set to zero, messages will not be displayed.

INTERNAL: ATTRIBUTES

Attributes are reserved for use by the autoconfiguration routines. There
is presently no user-level API at this time to access attributes for a
particular device.  The BSP-specific device exclusion routine affects 
the attributes indirectly by specifying which devices are to be excluded 
from the scan and configuration process.

Attributes are divided into device attributes and bridge attributes.  The first 
group below describes device attributes.

.IP "PCI_AUTO_ATTR_DEV_EXCLUDE" 32
Specifies that a device is to be excluded from the automatic scan
and configuration process
.IP "PCI_AUTO_ATTR_DEV_DISPLAY" 32
Specifies that a device is a display device
.IP "PCI_AUTO_ATTR_DEV_PREFETCH" 32
Specifies that a device has requested Prefetchable PCI memory
.LP

The second group below describes Bridge attributes. 

.IP "PCI_AUTO_ATTR_BUS_PREFETCH" 32
Specifies that the bridge device supports Prefetchable Memory behind the bridge
.IP "PCI_AUTO_ATTR_BUS_PCI" 32
Specifies that the bridge device is a PCI-to-PCI bridge and implements a PCI bus
.IP "PCI_AUTO_ATTR_BUS_HOST" 32
Specifies that the bridge device is a PCI Host bridge and implements a PCI bus
.IP "PCI_AUTO_ATTR_BUS_ISA" 32
Specifies that the bridge device is an ISA bridge implements an ISA bus
.IP "PCI_AUTO_ATTR_BUS_4GB_IO" 32
Specifies that the bridge device supports 32-bit I/O Addressing
behind the bridge
.LP

INTERNAL: ATTRIBUTE INHERITANCE

Devices that reside on a particular bus automatically inherit the attributes 
of the bridge (Host or PCI-to-PCI) that implements that bus. This allows
devices to take advantage of the fact that, for example, a PCI-to-PCI bridge
implements full 32-bit PCI I/O. Note that device attributes, such as the
inclusion attribute, are not inherited.

*/


/* includes */

#include "vxWorks.h"
#include "logLib.h"
#include "taskLib.h"
#include "string.h"
#include "dllLib.h"
#include "config.h"

#include "drv/pci/pciConfigLib.h"
#if 0
#include "drv/pci/pciAutoConfigLib.h"
#else
#include "./pciAutoConfigLib.h"
#endif

/* local defines */

#define PCI_CONFIG_ABSENT_F 0xffff
#define PCI_CONFIG_ABSENT_0 0x0000

/* local configuration defines */

#define PCI_AUTO_STATIC_LIST

#undef PCI_AUTO_RECLAIM_LIST

#ifndef PCI_AUTO_MAX_FUNCTIONS
# define PCI_AUTO_MAX_FUNCTIONS 32
#endif /* PCI_AUTO_MAX_FUNCTIONS */

IMPORT FUNCPTR _func_logMsg;

#ifdef PCI_AUTO_DEBUG
#define PCI_AUTO_DEBUG_MSG(s, a, b, c, d, e, f)\
{\
	LOCAL char dbgMsg[100];\
	if((a==0)&&(b==0)&&(c==0)&&(d==0)&&(e==0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r");\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b==0)&&(c==0)&&(d==0)&&(e==0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r",a);\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b!=0)&&(c==0)&&(d==0)&&(e==0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r",a,b);\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b!=0)&&(c!=0)&&(d==0)&&(e==0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r",a,b,c);\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b!=0)&&(c!=0)&&(d!=0)&&(e==0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r",a,b,c,d);\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b!=0)&&(c!=0)&&(d!=0)&&(e!=0)&&(f==0))\
	{\
	sprintf(dbgMsg, s"\r",a,b,c,d,e);\
    sysDebugMsg(dbgMsg, 0);\
    }\
	if((a!=0)&&(b!=0)&&(c!=0)&&(d!=0)&&(e!=0)&&(f!=0))\
	{\
	sprintf(dbgMsg, s"\r",a,b,c,d,e,f);\
    sysDebugMsg(dbgMsg, 0);\
    }\
}
#else
#define PCI_AUTO_DEBUG_MSG(s, a, b, c, d, e, f)
#endif
/*#define PCI_AUTO_DEBUG_MSG(s, a, b, c, d, e, f) \
    { \
    if ((pciAutoDebug == TRUE) && (_func_logMsg != NULL)) \
        { \
	(*_func_logMsg)(s, a, b, c, d, e, f); \
        taskDelay(10); \
        } \
    }*/

/* typedefs */

/* globals */

#ifdef PCI_AUTO_DEBUG
BOOL pciAutoDebug = TRUE;
#else
BOOL pciAutoDebug = FALSE;
#endif

IMPORT int pciMaxBus;

/* locals */

#ifdef PCI_AUTO_STATIC_LIST
LOCAL PCI_LOC pciAutoLocalFuncList[PCI_AUTO_MAX_FUNCTIONS];
#endif

LOCAL int lastPciListSize;
LOCAL PCI_LOC *pLastPciList;

LOCAL UCHAR pciAutoIntRoutingTable[4] = { (UCHAR) 0xff,
                                      (UCHAR) 0xff,
                                      (UCHAR) 0xff,
                                      (UCHAR) 0xff
                                    };
/* forward declarations */

LOCAL PCI_LOC * pciAutoListCreate ( PCI_SYSTEM * pSystem, int *pListSize);
LOCAL UINT pciAutoBusProbe ( PCI_SYSTEM * pSystem, UINT priBus,
    UINT secBus, PCI_LOC*  pPciLoc, PCI_LOC** ppPciList,
    int * pListSize);
LOCAL UINT pciAutoDevProbe ( PCI_SYSTEM * pSystem, UINT bus,
    UCHAR offset, UCHAR inheritAttrib, PCI_LOC **ppPciList, int * pListSize);
LOCAL void pciAutoFuncConfigAll ( PCI_SYSTEM * pSystem,
    PCI_LOC *pPciList, UINT nSize);
LOCAL void pciAutoDevConfig ( PCI_SYSTEM * pSystem, UINT bus,
    PCI_LOC **ppPciList, UINT *nSize);
LOCAL void pciAutoFuncConfig ( PCI_SYSTEM * pSystem, PCI_LOC * pPciFunc);
LOCAL void pciAutoBusConfig ( PCI_SYSTEM * pSystem, PCI_LOC * pPciLoc,
    PCI_LOC **ppPciList, UINT *nSize);

/* subroutines */

/******************************************************************************
*
* pciAutoConfig - Automatically configure all nonexcluded PCI headers.
*
* Top level function in the PCI configuration process:
*
* For all nonexcluded PCI functions on all PCI bridges, this routine
* will automatically configure the PCI configuration headers for PCI
* devices and subbridges.  The fields that are programmed are:
*
* .IP 1. 4
* Status register.
* .IP 2. 4
* Command Register.
* .IP 3. 4
* Latency timer.
* .IP 4. 4
* Cache Line size.
* .IP 5. 4
* Memory and/or I/O base address and limit registers.
* .IP 6. 4
* Primary, secondary, subordinate bus number (for PCI-PCI bridges).
* .IP 7. 4
* Expansion ROM disable.
* .IP 8. 4
* Interrupt Line.
* .LP
*
* ALGORITHM:
*
* Probe PCI config space and create a list of available PCI functions.
* Call device exclusion function, if registered, to exclude/include device.
* Disable all devices before we initialize any.
* Allocate and assign PCI space to each device.
* Calculate and set interrupt line value.
* Initialize and enable each device.
*
* RETURNS: N/A.
*
*/

void pciAutoConfig
    (
    PCI_SYSTEM * pSystem	/* PCI system to configure */
    )
    {
    PCI_LOC* pPciList;		/* Pointer to PCI include list	*/
    int listSize;		/* Size of PCI include list	*/

    /* Input parameter sanity checking */

    if (pSystem == NULL)
	{
	return;
	}

    while (TRUE)
        {

        /*
         * Probe all PCI busses dynamically creating a function list
         * of all functions found. Excluded devices are skipped over.
         */

        pPciList = pciAutoListCreate (pSystem, &listSize);

	if ( pSystem->pciRollcallRtn == NULL )