rtlcpp.h

MPC8241:本程序是freescale的824*系列的BSP源程序

#define RTL_PHY_ANEXP			0x06

#define RTL_PHY_ANAR_NEXTPAGE	0x8000
#define RTL_PHY_ANAR_RSVD0		0x4000
#define RTL_PHY_ANAR_TLRFLT		0x2000
#define RTL_PHY_ANAR_RSVD1		0x1000
#define RTL_PHY_ANAR_RSVD2		0x0800
#define RTL_PHY_ANAR_RSVD3		0x0400
#define RTL_PHY_ANAR_100BT4		0x0200
#define RTL_PHY_ANAR_100BTXFULL	0x0100
#define RTL_PHY_ANAR_100BTXHALF	0x0080
#define RTL_PHY_ANAR_10BTFULL	0x0040
#define RTL_PHY_ANAR_10BTHALF	0x0020
#define RTL_PHY_ANAR_PROTO4		0x0010
#define RTL_PHY_ANAR_PROTO3		0x0008
#define RTL_PHY_ANAR_PROTO2		0x0004
#define RTL_PHY_ANAR_PROTO1		0x0002
#define RTL_PHY_ANAR_PROTO0		0x0001

/*
 * These are the register definitions for the PHY (physical layer
 * interface chip).
 */
/*
 * PHY BMCR Basic Mode Control Register
 */

#define RTL_PHY_BMCR_RESET			0x8000
#define RTL_PHY_BMCR_LOOPBK			0x4000
#define RTL_PHY_BMCR_SPEEDSEL		0x2000
#define RTL_PHY_BMCR_AUTONEGENBL		0x1000
#define RTL_PHY_BMCR_RSVD0			0x0800	/* write as zero */
#define RTL_PHY_BMCR_ISOLATE		0x0400
#define RTL_PHY_BMCR_AUTONEGRSTR		0x0200
#define RTL_PHY_BMCR_DUPLEX			0x0100
#define RTL_PHY_BMCR_COLLTEST		0x0080
#define RTL_PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */

/*
 * RESET: 1 == software reset, 0 == normal operation
 * Resets status and control registers to default values.
 * Relatches all hardware config values.
 *
 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
 *
 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
 * Link speed is selected byt his bit or if auto-negotiation if bit
 * 12 (AUTONEGENBL) is set (in which case the value of this register
 * is ignored).
 *
 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
 * determine speed and mode. Should be cleared and then set if PHY configured
 * for no autoneg on startup.
 *
 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
 *
 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
 *
 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
 *
 * COLLTEST: 1 == collision test enabled, 0 == normal operation
 */

/* 
 * PHY, BMSR Basic Mode Status Register 
 */   
#define RTL_PHY_BMSR_100BT4			0x8000
#define RTL_PHY_BMSR_100BTXFULL		0x4000
#define RTL_PHY_BMSR_100BTXHALF		0x2000
#define RTL_PHY_BMSR_10BTFULL		0x1000
#define RTL_PHY_BMSR_10BTHALF		0x0800
#define RTL_PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
#define RTL_PHY_BMSR_MFPRESUP		0x0040
#define RTL_PHY_BMSR_AUTONEGCOMP	0x0020
#define RTL_PHY_BMSR_REMFAULT		0x0010
#define RTL_PHY_BMSR_CANAUTONEG		0x0008
#define RTL_PHY_BMSR_LINKSTAT		0x0004
#define RTL_PHY_BMSR_JABBER			0x0002
#define RTL_PHY_BMSR_EXTENDED		0x0001

/* ethernet media */

#define IFM_ETHER		0x00000020
#define	IFM_10_T		3		/* 10BaseT - RJ45 */
#define	IFM_10_2		4		/* 10Base2 - Thinnet */
#define	IFM_10_5		5		/* 10Base5 - AUI */
#define	IFM_100_TX		6		/* 100BaseTX - RJ45 */
#define	IFM_100_FX		7		/* 100BaseFX - Fiber */
#define	IFM_100_T4		8		/* 100BaseT4 - 4 pair cat 3 */
#define	IFM_100_VG		9		/* 100VG-AnyLAN */
#define	IFM_100_T2		10		/* 100BaseT2 */

/* Shared media sub-types */

#define	IFM_AUTO		0	/* Autoselect best media */
#define	IFM_MANUAL		1	/* Jumper/dipswitch selects media */
#define	IFM_NONE		2	/* Deselect all media */

/* Shared options */

#define IFM_FDX			0x00100000	/* Force full duplex */
#define	IFM_HDX			0x00200000	/* Force half duplex */
#define IFM_FLAG0		0x01000000	/* Driver defined flag */
#define IFM_FLAG1		0x02000000	/* Driver defined flag */
#define IFM_FLAG2		0x04000000	/* Driver defined flag */
#define	IFM_LOOP		0x08000000	/* Put hardware in loopback */

/* Masks */

#define	IFM_NMASK		0x000000e0	/* Network type */
#define	IFM_TMASK		0x0000000f	/* Media sub-type */
#define	IFM_IMASK		0xf0000000	/* Instance */
#define	IFM_ISHIFT		28		/* Instance shift */
#define	IFM_OMASK		0x0000ff00	/* Type specific options */
#define	IFM_GMASK		0x0ff00000	/* Global options */

/* Status bits */

#define	IFM_AVALID		0x00000001	/* Active bit valid */
#define	IFM_ACTIVE		0x00000002	/* Iface bound to working net */

/*
 * Macros to extract various bits of information from the media word.
 */
#define	IFM_TYPE(x)	((x) & IFM_NMASK)
#define	IFM_SUBTYPE(x)	((x) & IFM_TMASK)
#define	IFM_INST(x)	(((x) & IFM_IMASK) >> IFM_ISHIFT)

#define RTL_FLAG_FORCEDELAY	1
#define RTL_FLAG_SCHEDDELAY	2
#define RTL_FLAG_DELAYTIMEO	3	


/* The definition of the driver control structure */

typedef struct rtl_device
    {	
    END_OBJ     end;			/* The class we inherit from. */
    rtl_ib       *ib;			/* ptr to Initialization Block */
    UINT8		devType;	    /* 8129, 8139A or 8139B  OR 8139C*/
    int			unit;			/* unit number */
    UINT8		phy_addr;		/* PHY address */
    int         rmdIndex;               /* current RMD index */
	int         tmdIndex;               /* current TMD index */
	int         tmdIndexC;               /* complete TMD index */
    /* int		nextDesc; */ /* Next Tx Descriptor */
	/* int		freeDesc; */	/* Free Tx Descriptors */
	/* char		*pDescMem[RTL_NUM_TX_DESC]; */ /* Pointer to buffer */
    /* char 	txmemspace[RTL_NUM_TX_DESC * RTL81x9_BUFSIZE]; */
    /* int		rmdNext; */		/* index into the next Rx Pkt */
    int			tmdNext;		/* index into the next Tx Pkt */	
    char		*ptrRxBufSpace;	/* Ptr to the Rx Buffer Pool */
    char		*ptrTxBufSpace;	/* Ptr to the Tx Buffer Pool */	
    int			rringSize;		/* RMD ring size */
    int 		rringLen; 		/* RMD ring length (bytes) */
	int 		tringLen; 		/* TMD ring length (bytes) */
	int         tringSize;              /* TMD ring size */
    RTL_RMD		*pRring;		/* RMD ring start */
	RTL_TMD		*pTring;		/* RMD ring start */
    int         ivec;           /* interrupt vector */
    int         ilevel;         /* interrupt level */
    UINT32		devAdrs;		/* device register RAP */
    UINT16		csr3B;			/* csr3 value board specific */
    char*       pShMem;         /* real ptr to shared memory */
    char*       memBase;        /* RTL memory pool base */
    char*       memAdrs;        /* RTL memory pool base */
    int         memSize;        /* RTL memory pool size */
    int         memWidth;       /* width of data port */
    int         offset;
    int         csr0Errs;       /* count of csr0 errors */
    UINT32      flags;			/* Our local flags */
    UINT32		pciMemBase;		/* memory base as seen from PCI*/
    UCHAR		enetAddr[6];	/* ethernet address */
    CACHE_FUNCS cacheFuncs;     /* cache function pointers */
    BOOL		txBlocked; 		/* transmit flow control */
    CL_POOL_ID  pClPoolId;
    END_ERR     lastError;      /* Last error passed to muxError */
    BOOL        errorHandling;  /* task level error handling */
    u_short     errorStat;      /* error status */
    UINT32      reg_rcr;	/* RCR for reset */
	int         proc_rx		;
	char		*freeData[128];
    } RTL81X9END_DEVICE;



/* Configuration items */

#define RMD_SIZ	sizeof(RTL_RMD)
#define IB_SIZ	sizeof(rtl_ib)

#ifdef __cplusplus
}
#endif

#endif /* __INCrtl81x9Endh */
/****************************************************************/
/*for CPP*/

/* for polling */
#define RTLCP_HPQ 		0x80
#define RTLCP_NPQ 		0x40
#define RTLCP_FSWINT 	0x01


/* descriptor */
#define RTLCP_RX_OWN  	0x80000000
#define RTLCP_RX_EOR  	0x40000000
#define RTLCP_RX_FS  	0x20000000
#define RTLCP_RX_LS 	0x10000000
#define RTLCP_RX_EMS 	0x10040000
#define RTLCP_RX_RES 	0x10080000





descript * txdescri;
descript * rxdescri;
#define RTLCP_MAX_RX_DESC 32
#define RTLCP_MAX_TX_DESC 32
#define CPRX	0x0002	/* enable cplus rx mode */
#define CPTX	0x0001	/* enable cplus tx mode */
#define CPMULRX 0x0008    /* enable cplus PCI multiple Read/Write */	



/***************************ln********************/
#define RTL_RMD_BUF_TO_ADDR(rmd, tmp, buf) \
	tmp = (void *)RTL_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
	rmd->bufptr0 = (UINT32)PCI_SWAP (tmp);

#define RTL_TMD_BUF_TO_ADDR(tmd, tmp, buf) \
	tmp = (void *)RTL_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
    tmd->bufptr0 = (ULONG)PCI_SWAP (tmp);

#define RTL_TMD_TO_ADDR(tmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (tmd->bufptr0)); \
        addr = RTL_CACHE_PHYS_TO_VIRT(pTemp);		\
	}

#define RTL_RMD_TO_ADDR(rmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (rmd->bufptr0)); \
        addr = (char *)(RTL_CACHE_PHYS_TO_VIRT(pTemp));		\
	}

#define RTL_ADDR_TO_TMD(addr, tmd) \
	{	\
	UINT32 pTemp = RTL_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	tmd->tBufAddr = PCI_SWAP (addr); \
	}

#define RTL_ADDR_TO_RMD(addr, rmd) \
	{ \
	UINT32 pTemp = RTL_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	rmd->rBufAddr = PCI_SWAP (addr); \
	}



/* Set address of receiver descriptor ring and size in init block */

	
/* Set address of transmitter descriptor ring and size in init block */


/* clear the logical address filter */
    


/* set the logical address filter to accept a new multicast address */














/*******************************************************/
/* device macros to read/write descriptor, initialization blocks, etc. */

#define RTL_RMD_BUF_TO_ADDR(rmd, tmp, buf) \
	tmp = (void *)RTL_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
	rmd->bufptr0 = (UINT32)PCI_SWAP (tmp);

#define RTL_TMD_BUF_TO_ADDR(tmd, tmp, buf) \
	tmp = (void *)RTL_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
    tmd->bufptr0 = (ULONG)PCI_SWAP (tmp);

#define RTL_TMD_TO_ADDR(tmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (tmd->bufptr0)); \
        addr = RTL_CACHE_PHYS_TO_VIRT(pTemp);		\
	}

#define RTL_RMD_TO_ADDR(rmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (rmd->bufptr0)); \
        addr = (char *)(RTL_CACHE_PHYS_TO_VIRT(pTemp));		\
	}

#define RTL_ADDR_TO_TMD(addr, tmd) \
	{	\
	UINT32 pTemp = RTL_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	tmd->tBufAddr = PCI_SWAP (addr); \
	}

#define RTL_ADDR_TO_RMD(addr, rmd) \
	{ \
	UINT32 pTemp = RTL_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	rmd->rBufAddr = PCI_SWAP (addr); \
	}



/* Set address of receiver descriptor ring and size in init block */

	
/* Set address of transmitter descriptor ring and size in init block */


/* Cache macros */

#define RTL_CACHE_INVALIDATE(address, len) \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))

#define RTL_CACHE_VIRT_TO_PHYS(address) \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheFuncs, (address))

#define RTL_CACHE_PHYS_TO_VIRT(address) \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheFuncs, (address))

/* memory to PCI address translation macros */

#define PCI_TO_MEM_PHYS(pciAdrs) \
    ((pciAdrs) - (pDrvCtrl->pciMemBase))
	
#define MEM_TO_PCI_PHYS(memAdrs) \
    ((memAdrs) + (pDrvCtrl->pciMemBase))