rtlcpp.h

MPC8241:本程序是freescale的824*系列的BSP源程序

/* Status 	- Offset 003Eh-003Fh - R/W */

#define RTL_IPT_PCI_ERR			0x8000
#define RTL_IPT_PCS_TIMEOUT		0x4000		/* 8129 only */
#define RTL_IPT_CABLE_LEN_CHG	0x2000
#define RTL_IPT_RX_FIFO_OVER	0x40		/* 8139 only */
#define RTL_IPT_RX_UNDERUN		0x20
#define RTL_IPT_RX_OVERFLOW		0x10
#define RTL_IPT_TX_ERR			0x08
#define RTL_IPT_TX_OK			0x04
#define RTL_IPT_RX_ERR			0x02
#define RTL_IPT_RX_OK			0x01

/*#define RTL_VALID_INTERRUPTS	0xe07f*/	/* All Interrupts above */
#define RTL_VALID_INTERRUPTS	0x006f	    /* modify by zoutl 2003-4-7 16:28 */

/*#define RTL_ERROR_INTERRUPTS	0x807a*/	/* All bar OK's, TOUT and LEN_CHG */
#define RTL_ERROR_INTERRUPTS	0x007a  /*vicadd*/

#define RTL_RX_INTERRUPTS		0x73
#define RTL_TX_INTERRUPTS		0x0c
#define RTL_CONFIG_INTERRUPTS	0xe000 /* PCI,PCS,CABLE */
								

/* Transmit Config Regs */
/* Offset 0040-0043 */

#define RTL_TXCG_HWVER			0x80000000 /* 7 for RTL8139 (A and B) */
										   /* 6 for RTL8139 */

#define RTL_TXCG_BLID			0x40000000 /* DevType 0 - A 1 - B) */

#define RTL_TXCG_LBK1			0x40000		/* Loopback Test */
#define RTL_TXCG_LBK0			0x20000		/* 00 - Normal */
											/* 01 - MAC */
											/* 10 - PHY */
											/* 11 - Twister */

#define RTL_TXCG_CRC			0x10000		/* Append CRC */

#define RTL_TXCG_MXDMA2			0x400		/* Max DMA Burst Size */
#define RTL_TXCG_MXDMA1			0x200		/* 000 - 16   001 - 32   */
#define RTL_TXCG_MXDMA0			0x100		/* 010 - 64	  011 - 128  */
											/* 100 - 256  101 - 512  */
											/* 110 - 1024 111 - 2048 */

#define RTL_TXCG_TXRR			0x80		/* Retry Count - 16 * TXRR */

#define RTL_TXCG_CLRABT			0x01		/* Re transmit */

#define RTL_TXCG_MAXDMA			0x00000700	/* max DMA burst size */
#define RTL_TXCG_LOOPBKTST		0x00060000	/* loopback test */
#define RTL_TXCG_IFG			0x03000000	/* interframe gap */


/* Receive Configuration Register */
/* Offset 0044-0047h */


#define RTL_RXCG_ERTH			0x40000		/* Early Rx Threshold Multiplier */
											/* 0 - None 1 - 1/16 2 - 2/16	 */
											/* etc. etc. 					 */

#define RTL_RXCG_MULERINT		0x20000		/* Multiple Early interrupt */
#define RTL_RXCG_RER8			0x10000		/* Rx Packet Length Error	*/

#define RTL_RXCG_RXFTH2			0x8000		/* Rx FIFO Threshold in Bytes */
#define RTL_RXCG_RXFTH1			0x4000		/* 000 - 16   , 001 - 32   */
#define RTL_RXCG_RXFTH0			0x2000		/* 010 - 64   , 011 - 128  */
											/* 100 - 256  , 101 - 512  */
											/* 110 - 1024 , 111 - none */

#define RTL_RXCG_RBLEN1			0x1000		/* Rx Buffer Length			*/
#define RTL_RXCG_RBLEN0			0x800		/* 00 - 8k  + 16bytes */
											/* 01 - 16k + 16bytes */
											/* 10 - 32k + 16bytes */
											/* 11 - 64k + 16bytes */

#define RTL_RXCG_MXDMA2			0x400		/* Max DMA Burst size per RX DMA */
#define RTL_RXCG_MXDMA1			0x200		/* 000 - 16   , 001 - 32   */
#define RTL_RXCG_MXDMA0			0x100		/* 010 - 64   , 011 - 128  */								      
											/* 100 - 256  , 101 - 512  */
											/* 110 - 1024 , 111 - unlimited */

#define RTL_RXCG_WRAP			0x80			
#define RTL_RXCG_9356SEL		0x40		/* Selects EEPROM 1 - 9356 0 - 9346 */			
#define RTL_RXCG_AER			0x20		/* Accept Error Packet */			
#define RTL_RXCG_AR				0x10		/* Accept RUNT */			
#define RTL_RXCG_AB				0x08		/* Accept Broadcast */			
#define RTL_RXCG_AM				0x04		/* Accept Multicast */			
#define RTL_RXCG_APM			0x02		/* Accept Physical match */			
#define RTL_RXCG_AAP			0x01		/* Accept all Phy */			

/* The following are used as the initial Tx and Rx Configs */

/*#define RTL_RXCFG_CONFIG 	(RTL_RX_BUF_SZ|RTL_RX_FIFOTHRESH|RTL_RX_MAXDMA)*/
#define RTL_RXCFG_CONFIG 	(RTL_RX_BUF_SZ|RTL_RX_FIFOTHRESH|RTL_RX_MAXDMA)
#define RTL_TXCFG_CONFIG	(RTL_TXCG_IFG|RTL_TX_MAXDMA)


/* 9346CR Command Register */
/* Offset 0050h - R/W */

#define RTL_EEMODE_PROGRAM		0x80		/* 8139B Operating Mode */
#define RTL_EEMODE_AUTOLOAD		0x40		/* 00 - Normal */
											/* 01 - Auto Load */
											/* 10 - 93c46 Prog Mode */
											/* 11 - Cfg Reg Write Mode */
#define RTL_EEMODE_WRITECFG		(0x80|0x40)
#define RTL_EEMODE_OFF			0x00

/* MII register (8129 only) */
/* Offset 005Ah - R/W */

#define RTL_MII_CLK			0x01
#define RTL_MII_DATAIN		0x02
#define RTL_MII_DATAOUT		0x04
#define RTL_MII_DIR			0x80	/* 0 == input, 1 == output */

/*
 * EEPROM control register
 */

#define RTL_EE_DATAOUT			0x01		/* Data out */
#define RTL_EE_DATAIN			0x02		/* Data in */
#define RTL_EE_CLK				0x04		/* clock */
#define RTL_EE_SEL				0x08		/* chip select */
#define RTL_EE_MODE				(0x40|0x80)

/* 9346 EEPROM commands */
#define RTL_EECMD_WRITE			0x140
#define RTL_EECMD_READ			0x180
#define RTL_EECMD_ERASE			0x1c0

#define RTL_EECMD_EWEN			0x130
#define RTL_EECMD_EWDS			0x100

#define RTL_EE_ID				0x00
#define RTL_EE_PCI_VID			0x01
#define RTL_EE_PCI_DID			0x02

/* Location of station address inside EEPROM */
#define RTL_EE_EADDR			0x07




/* Configuration Register 0 */
/* Offset 0051h - R/W */

#define RTL_CONFIG0_BS2			0x04		/* Boot ROM Size */
#define RTL_CONFIG0_BS1			0x02		/* 000 - No  Boot Rom */
#define RTL_CONFIG0_BS0			0x01		/* 001 - 8k  Boot Rom */
											/* 010 - 16k Boot Rom */
											/* 011 - 32k Boot Rom */
											/* 100 - 64k Boot Rom */
											/* 101 - 128 Boot Rom */
											/* 110 - unused */
											/* 111 - unused */

/* Configuration Register 1 */
/* Offset 0052h - R/W */

#define RTL_CONFIG1_LEDS1		0x80		/* LED's */
#define RTL_CONFIG1_LEDS0		0x40		/* Refer to LED IFace */
#define RTL_CONFIG1_DVRLOAD		0x20		/* Driver loaded status bit */
#define RTL_CONFIG1_LWACT		0x10		/* LWAKE Active mode */
#define RTL_CONFIG1_MEMMAP		0x08		/* Registers Mapped to PCI Memory */
#define RTL_CONFIG1_IOMAP		0x04		/* Registers Mapped to PCI I/O space */
#define RTL_CONFIG1_VPD			0x02		/* Vital Product Data */
#define RTL_CONFIG1_PMEN		0x01		/* Power Management Enable */

/* Media Status Bits 	*/
/* Offset 0058h - R/W 	*/

#define RTL_MED_RXPF				0x01	/* Rx Pause Flag */
#define RTL_MED_TXPF				0x02	/* Tx Pause Flag */
#define	RTL_MED_LINKB				0x04	/* Inverse of Link Status */
											/* 0 - Link OK */
#define	RTL_MED_SPEED				0x08    /* 1 - 10Mbps, 0 - 100Mbps */
#define RTL_MED_AUX					0x10	/* Aux power Status */
#define	RTL_MED_RXFCE				0x40	/* Rx Flow Control enable */
#define	RTL_MED_TXFCE				0x80	/* Tx Flow control enable */

/* Configuration Register 3	*/
/* Offset 0059h - R/W 		*/

#define RTL_CONFIG3_GNTSEL			0x80	/* Grant Select */
#define RTL_CONFIG3_PARM_EN			0x40	/* Paramater Enable - 100Mbps only */
#define RTL_CONFIG3_MAGIC			0x20	/* Magic Packet */
#define RTL_CONFIG3_LINKUP			0x10
#define RTL_CONFIG3_CARDB_EN		0x08	/* Card Bus Enable */
#define RTL_CONFIG3_CLKRUN_EN		0x04
#define RTL_CONFIG3_FUNCREG_EN		0x02	/* Functions registers enable */
#define RTL_CONFIG3_FBTBEN			0x01	/* Fast back to back enable */

/* Configuration Register 4 */
/* Offset 005Ah - R/W 		*/

#define RTL_CONFIG4_RXFIFO_CLR		0x80	/* Automatically clear RX FIFO OFlow */
#define RTL_CONFIG4_ANAOFF			0x40	/* Analogue Power Off */
#define RTL_CONFIG4_LONGWF			0x20	/* Long Wake up Frame */
#define RTL_CONFIG4_LWPME			0x10	/* LANWAKE vs PMEB */
#define RTL_CONFIG4_MSWFB			0x08	/* Microsoft Wake up frame */
#define RTL_CONFIG4_LWPTN			0x04	/* LWAKE Pattern */
#define RTL_CONFIG4_PARM_EN2		0x02	/* Parameter Enable 2  */
#define RTL_CONFIG4_RD_AUX			0x01	/* Rev d - Aux Power Status */


/* Transmit Status of all Descriptors */
/* Offset 0060 - 0061h - R/W 		  */
/* RTL_REGS_TX_SUMMARY			      */

#define RTL_TSAD_TOK_MSK			0xf000	/* Tx Ok Descs          */
#define RTL_TSAD_TUN_MSK			0x0f00	/* Tx Underrun Descs    */
#define RTL_TSAD_TABT_MSK			0x00f0	/* Transmit Abort Descs */
#define RTL_TSAD_OWN_MSK			0x000f	/* OWN Bit Descriptors  */

/* Basic Mode Control Register 	*/
/* Offset 0062-0063h - R/W 		*/
/* Note : All Default are 0 	*/

#define	RTL_BMCR_RESET				0x8000	/* Sets Status and Control Regs */
											/* 1=Software reset 0=normal op */

#define	RTL_BMCR_SPD_SET			0x2000	/* Network Speed */
											/* 1=100Mbps, 0=10Mbps */

#define	RTL_BMCR_ANE				0x1000	/* Auto Negotiation Enable */
#define	RTL_BMCR_RAN				0x0200	/* Restart Auto Negotiation */
#define	RTL_BMCR_DUPX				0x0100	/* Duplex mode */
											/* 1=full duplex, 0=normal */
/* Basic Mode Status Register 	*/
/* Offset 0064-0065h - R/W 		*/

#define	RTL_BMSR_100BASE_T4			0x8000	/* 1=enable, default = 0 */
#define	RTL_BMSR_100BASE_TX_FDUPX	0x4000	/* 1=enable, default = 1 */
#define	RTL_BMSR_100BASE_TX_HDUPX	0x2000	/* 1=enable, default = 1 */
#define	RTL_BMSR_10BASE_T_FDUPX		0x1000	/* 1=enable, default = 1 */
#define	RTL_BMSR_10BASE_T_HDUPX		0x0800	/* 1=enable, default = 1 */

#define	RTL_BMSR_AUTO_NEG_COMP		0x0020	/* 1=completed,   default = 0 */
#define	RTL_BMSR_REMOTE_FAULT		0x0010	/* 1=detected,    default = 0 */
#define	RTL_BMSR_AUTO_NEG_FAIL		0x0008	/* 1=failed,      default = 1 */
#define	RTL_BMSR_LINK_STATUS		0x0004	/* 1=established, default = 0 */
#define	RTL_BMSR_JABBER_DETECT		0x0002	/* 1=detected,    default = 0 */
#define	RTL_BMSR_EXT_CAPABILITY		0x0001	/* 1=extended,    default = 1 */
											/* 0=basic regs */

/* Auto Negotiation Advertisement Register 	*/
/* Offset 0066-0067h - R/W 		*/

#define	RTL_ANAR_NP			0x8000	/* Next Page Bit */
									/* 0=primary capability data page 	*/
									/* 1=protocol specific data page	*/
									/* default = 0 */

#define	RTL_ANAR_ACK		0x4000	/* 1=acknowledge, default = 0 */

#define	RTL_ANAR_RF			0x2000	/* 1=advertise remote fault detection	*/
									/*  default = 0 */

#define	RTL_ANAR_PAUSE		0x0400	/* 1=flow control supported locally */
									/* default comes from EEPROM */

#define	RTL_ANAR_T4			0x0200	/* 1=100Base-T4 supported */
									/* default = 0 */

#define	RTL_ANAR_TXFD		0x0100	/* 1=100Base-Tx full duplex supported */
									/* default = 1 */

#define	RTL_ANAR_TX			0x0080	/* 1=100Base-Tx supported */
									/* default = 1 */

#define	RTL_ANAR_10FD		0x0040	/* 1=10Base-T full duplex supported */
									/* default = 1 */

#define	RTL_ANAR_10			0x0020	/* 1=10Base-T supported */
									/* default = 1 */

#define	RTL_ANAR_SELECTOR	0x0001	/* Binary Encoded Selector */
									/* Currently only CSMA/CD <00001> */
									/* Supported */
									/* default = 00001 */

/*  EEPROM_Ctrl bits. */

/* eeprom contents */
    
#define RTL_EE_OEM_ADR0		0x0E
#define	RTL_EE_OEM_ADR1		0x11
#define RTL_EE_OEM_ADR2		0x13

#define	RTL_VENDOR_ID		0x10ec
#define	RTL_VENDOR_ID_MIS	0x1113
#define	RTL_8129_DEV_ID		0x8129
#define	RTL_8139_DEV_ID 	0x8139
#define	RTL_MIS_DEV_ID 		0x1211

#define	RTL_DEV_MASK		0xffff
#define	RTL_IO_SIZE			0x80

#define RTL_TIMEOUT			100

#define RTL_WIN_0    		0

#define RTL_MIN_FBUF		100    /* Minimum size of the first buffer in a */
                               /* chain. */

typedef struct rtl_mii_frame {
	UINT8			mii_stdelim;
	UINT8			mii_opcode;
	UINT8			mii_phyaddr;
	UINT8			mii_regaddr;
	UINT8			mii_turnaround;
	USHORT			mii_data;
} RTL_MII_FRAME ;

/*
 * MII constants
 */

#define RTL_MII_STARTDELIM	0x01
#define RTL_MII_READOP		0x02
#define RTL_MII_WRITEOP		0x01
#define RTL_MII_TURNAROUND	0x02

/*
 * Texas Instruments PHY identifiers
 */
#define TI_PHY_VENDORID		0x4000
#define TI_PHY_10BT			0x501F
#define TI_PHY_100VGPMI		0x502F

/*
 * These ID values are for the NS DP83840A 10/100 PHY
 */
#define NS_PHY_VENDORID		0x2000
#define NS_PHY_83840A		0x5C0F

/*
 * Level 1 10/100 PHY
 */
#define LEVEL1_PHY_VENDORID	0x7810
#define LEVEL1_PHY_LXT970	0x000F

/*
 * Intel 82555 10/100 PHY
 */
#define INTEL_PHY_VENDORID	0x0A28
#define INTEL_PHY_82555		0x015F

/*
 * SEEQ 80220 10/100 PHY
 */
#define SEEQ_PHY_VENDORID	0x0016
#define SEEQ_PHY_80220		0xF83F


#define RTL_PHY_UNKNOWN			6

#define RTL_PHYADDR_MIN			0x00
#define RTL_PHYADDR_MAX			0x1F

#define RTL_PHY_BMCR			0x00
#define RTL_PHY_BMSR			0x01
#define RTL_PHY_VENID			0x02
#define RTL_PHY_DEVID			0x03
#define RTL_PHY_ANAR			0x04
#define RTL_PHY_LPAR			0x05