rtlcpp.h

MPC8241:本程序是freescale的824*系列的BSP源程序

/* rtl81x9End.h - RealTek RTL81x9 Fast Ethernet interface header */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,26jan00,dgy  Set the Early Rx Threshold within
				 the RTL_RXCFG_CONFIG
01a,29oct99,dgy  written
*/

#ifndef __INCrtl81x9Endh
#define __INCrtl81x9Endh

#ifdef __cplusplus
extern "C" {
#endif

/*******KONGFQ 2005.8.29******/
#define ALL_ETH_FRAME_ENABLE        0x2f    /***小于64Byte的帧不接收***/


/***** DEBUG MACROS *****/

#undef DRV_DEBUG

#define DRV_DEBUG 
#ifdef	DRV_DEBUG

#define DRV_DEBUG_OFF			0x0000
#define DRV_DEBUG_RX			0x0001
#define	DRV_DEBUG_TX			0x0002
#define DRV_DEBUG_INT			0x0004
#define	DRV_DEBUG_POLL			(DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
#define	DRV_DEBUG_POLL_RX		0x0008
#define	DRV_DEBUG_POLL_TX		0x0010
#define	DRV_DEBUG_LOAD			0x0020
#define	DRV_DEBUG_IOCTL			0x0040
#define	DRV_DEBUG_START			0x0080
#define	DRV_DEBUG_ERR			0x0100
#define DRV_DEBUG_POLL_REDIR	0x10000
#define	DRV_DEBUG_LOG_NVRAM		0x20000
#define DRV_DEBUG_ALL			0xfffff

/* NET_POOL rtl81x9NetPool; */

#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)				\
	if (rtl81x9Debug & FLG)			\
            logMsg(X0, X1, X2, X3, X4, X5, X6);

#define DRV_PRINT(FLG,X)										\
	if (rtl81x9Debug & FLG) logMsg X;

#else /*DRV_DEBUG*/

#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
#define DRV_PRINT(DBG_SW,X)

#endif /*DRV_DEBUG*/

/* DMA Definitions */

#define RTL_RXDMA_16BYTES		0x00000000
#define RTL_RXDMA_32BYTES		0x00000100
#define RTL_RXDMA_64BYTES		0x00000200
#define RTL_RXDMA_128BYTES		0x00000300
#define RTL_RXDMA_256BYTES		0x00000400
#define RTL_RXDMA_512BYTES		0x00000500
#define RTL_RXDMA_1024BYTES		0x00000600
#define RTL_RXDMA_UNLIMITED		0x00000700

#define RTL_RXFIFO_16BYTES		0x00000000
#define RTL_RXFIFO_32BYTES		0x00002000
#define RTL_RXFIFO_64BYTES		0x00004000
#define RTL_RXFIFO_128BYTES		0x00006000
#define RTL_RXFIFO_256BYTES		0x00008000
#define RTL_RXFIFO_512BYTES		0x0000A000
#define RTL_RXFIFO_1024BYTES	0x0000C000
#define RTL_RXFIFO_NOTHRESH		0x0000E000

#define RTL_TXDMA_16BYTES		0x00000000
#define RTL_TXDMA_32BYTES		0x00000100
#define RTL_TXDMA_64BYTES		0x00000200
#define RTL_TXDMA_128BYTES		0x00000300
#define RTL_TXDMA_256BYTES		0x00000400
#define RTL_TXDMA_512BYTES		0x00000500
#define RTL_TXDMA_1024BYTES		0x00000600
#define RTL_TXDMA_2048BYTES		0x00000700

/*
 * The RealTek doesn't use a fragment-based descriptor mechanism.
 * Instead, there are only four register sets, each or which represents
 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
 * packet buffer (32-bit aligned!) and we place the buffer addresses in
 * the registers so the chip knows where they are.
 *
 * For reception, there's just one large buffer where the chip stores
 * all received packets.
 */

/* Configuration items */

/* #define RTL_BUFSIZ      (ETHERMTU + ENET_HDR_REAL_SIZ + 6) */
#define RTL_BUFSIZ      (ETHERMTU + ENET_HDR_REAL_SIZ + 6 +8) /* modified by zoutl 2003-3-17 15:47 */
#define RTL_RMD_RLEN     6       /* ring size as a power of 2 -- 32 RMD's */ /*vicadd*/
#define RTL_SPEED        10000000



#define RTL_TMD_RLEN     6          /*modified by mashuyu*/

/* Definitions for the drvCtrl flags field */
/* The format for the Flags field is as follows */

/* The first 16 bits are allocated as being used 	*/
/* for miscellaneous flags. The second 16 bits   	*/
/* are used for setting the Early Rx Threshold 		*/
/* from within the string passed in initialisation 	*/
/* This allows the user to taylor performance 		*/
/* depending on their board without the need 		*/
 /* recomplile the driver source code.				*/

#define RTL_FLG_PROMISCUOUS_FLAG     0x01
#define RTL_FLG_MEM_ALLOC_FLAG       0x02
#define RTL_FLG_MODE_MEM_IO_MAP	     0x04   /* device registers memory mapped */
#define RTL_FLG_POLLING              0x08	/* polling flag */

#define RTL_RXBUF_8				0x00000000
#define RTL_RXBUF_16			0x00000800
#define RTL_RXBUF_32			0x00001000
#define RTL_RXBUF_64			0x00001800

#define RTL_RX_BUF_SZ		RTL_RXBUF_16   
#define RTL_RXBUFLEN		(1 << ((RTL_RX_BUF_SZ >> 11) + 13))


#define RTL_RX_FIFOTHRESH   RTL_RXFIFO_NOTHRESH

#define RTL_RX_MAXDMA		RTL_RXDMA_1024BYTES		/*/vicadd*/
#define RTL_TX_MAXDMA		RTL_TXDMA_1024BYTES		/*/vicadd*/

/* configuration items */

#define RTL_DEV_NAME 			"rtl"	/* device name *//*modified by mashuyu*/
#define RTL_DEV_NAME_LEN 		4	/*modified by mashuyu*/
#define RTL81x9_BUFSIZE			1536  	/* aligned packet size */
#define RTL_CRC_SIZE 			4
/*#define RTL_NUM_TX_DESC			4	*/	/* Number of Tx descriptor registers. */


/*
 * Initialization Block.
 * Specifies addresses of receive and transmit descriptor rings.
 */				  

typedef struct rtlIB
    {
    ULONG       rtlIBMode;		 /* mode register */
    UCHAR       rtlIBPadr [8];   /* PADR: bswapd ethnt phys address */
    UCHAR       rtlIBLadrf [8];  /* logical address filter */
    USHORT      rtlIBRdraLow;    /* RDRA: read ring lower address */
    USHORT      rtlIBRdraHigh;   /* RDRA: read ring upper address */
	USHORT      rtlIBTdraLow;    /* TDRA: read ring lower address cp */
    USHORT      rtlIBTdraHigh;   /* TDRA: read ring upper address cp */

    } rtl_ib;

#define RTL_ADDR_TO_IB_RMD(addr, ib, rsize) \
	ib->rtlIBRdraLow = (u_long) addr; \
	ib->rtlIBRdraHigh = (((u_long) addr >> 16) & 0xff) | (rsize << 13);

/* Receive Message Descriptor Entry.*/

typedef struct rtlRxData
    {
    USHORT      rxStatusFlags;
    USHORT      rxPktLen;
    UCHAR	   	*pktData;
    } RTL_RX_DATA;

typedef struct rtlRMD
    {
    /* USHORT      rxStatusFlags;
    USHORT      rxPktLen;
    UCHAR	   	*pktData; */
	UINT32 cmd_leng;
	UINT32 vlan;
	UINT32 bufptr0;	/* low address */
	UINT32 bufptr1;
	
    } RTL_RMD;

typedef struct rtlTMD
    {
		UINT32 cmd_leng;
		UINT32 vlan;
		UINT32 bufptr0;	/* low address */
		UINT32 bufptr1;
	
    } RTL_TMD;

typedef struct descript{
		UINT32 cmd_leng;
		UINT32 vlan;
		UINT32 bufptr0;	/* low address */
		UINT32 bufptr1;
		} descript;

/* clear the logical address filter */
    
#define RTL_ADDRF_CLEAR(pIb) (bzero(&(pIb)->rtlIBLadrf[0], 8))

/* set the logical address filter to accept a new multicast address */
    
#define RTL_ADDRF_SET(pIb, crc) \
    (((pIb)->rtlIBLadrf[((crc) & 0x0000003f) >> 3]) |= (1 << ((crc) & 0x7)))


/* This driver supports the following four variants of the RTL Fast */
/* Ethernet Controller Chip. 8129, 8139 - Single Chip Fast	*/
/* Ethernet Controller. 8139A=8139 with power saving. 8139B=8139A + Cardbus*/
/* PCI/CardBus support												*/
 
#define	RTL_DEV_8129	1
#define	RTL_DEV_8139A	2
#define	RTL_DEV_8139B	3
#define	RTL_DEV_8139C	4		/* almost like  8139C */
#define RTL_DEV_8139_CP 9

/*
 * RealTek PCI vendor ID
 */
#define	RTL_VENDORID				0x10EC

/*
 * RealTek chip device IDs.
 */
#define	RTL_DEVICEID_8129			0x8129
#define	RTL_DEVICEID_8139			0x8139

/*
 * Accton PCI vendor ID
 */





#if     _BYTE_ORDER==_BIG_ENDIAN
#define PCI_SWAP(x)		LONGSWAP((int)(x))
#define PCI_WORD_SWAP(x)	((LSB((USHORT)(x)) << 8) | MSB((USHORT)(x)))
#else
#define PCI_SWAP(x)		(x)
#define PCI_WORD_SWAP(x)	(x)
#endif


/*
 * Generic shared memory read and write macros.
 */

#ifndef SHMEM_RD
#    define SHMEM_RD(x)	*(x)
#endif

#ifndef SHMEM_WR
#    define SHMEM_WR(x,y)	(*(x) = y)
#endif

/* RTL81x9 Registers */

#define RTL_REGS_IDR0				0x00
#define RTL_REGS_IDR1				0x01
#define RTL_REGS_IDR2				0x02
#define RTL_REGS_IDR3				0x03
#define RTL_REGS_IDR4				0x04
#define RTL_REGS_IDR5				0x05
#define RTL_REGS_MAR0				0x08	/* Multicast filter. */
#define RTL_REGS_TX_STATUS0			0x10	
#define RTL_REGS_TX_STATUS1			0x14	
#define RTL_REGS_TX_STATUS2			0x18	
#define RTL_REGS_TX_STATUS3			0x1C	
#define RTL_REGS_TX_ADDR0			0x20
#define RTL_REGS_TX_START_NOR_0			0x20	/*c+ normal low*/
#define RTL_REGS_TX_ADDR1			0x24
#define RTL_REGS_TX_START_NOR_1			0x24	
#define RTL_REGS_TX_ADDR2			0x28
#define RTL_REGS_TX_START_HIGH_0			0x28	/* c+ high */
#define RTL_REGS_TX_ADDR3			0x2c
#define RTL_REGS_TX_START_HIGH_1		0x2c
#define RTL_REGS_RX_BUF				0x30
#define RTL_REGS_RX_EARLY_CNT		0x34
#define RTL_REGS_RX_EARLY_STATUS	0x36
#define RTL_REGS_CHIP_CMD			0x37
#define RTL_REGS_RX_BUF_PTR			0x38
#define RTL_REGS_RX_BUF_ADDR		0x3A
#define RTL_REGS_INTR_MASK			0x3C
#define RTL_REGS_INTR_STATUS		0x3E
#define RTL_REGS_TX_CONFIG			0x40
#define RTL_REGS_RX_CONFIG			0x44
#define RTL_REGS_TIMER				0x48	/* A general-purpose counter. */
#define RTL_REGS_RX_MISSED			0x4C	/* 24 bits valid, write clears. */
#define RTL_REGS_CFG_9346			0x50
#define RTL_REGS_CONFIG_0			0x51
#define RTL_REGS_CONFIG_1			0x52
#define RTL_REGS_TIMERINT			0x54
#define RTL_REGS_MSR				0x58
#define RTL_REGS_CONFIG3			0x59
#define RTL_REGS_MII				0x5A		/* 8129 chip only */
#define RTL_REGS_MULTI_INTR			0x5C
#define RTL_REGS_PCI_RERID			0x5e
#define RTL_REGS_TX_SUMMARY			0x60
#define RTL_REGS_MII_BMCR			0x62
#define RTL_REGS_MII_BMSR			0x64
#define RTL_REGS_NWAY_ADVERT		0x66
#define RTL_REGS_NWAY_LPAR			0x68
#define RTL_REGS_NWAY_EXPANSION		0x6A
#define RTL_REGS_DIS				0x6c
#define	RTL_REGS_FCSC				0x6e
#define RTL_REGS_NWAYTR				0x70	/* N-Way Test Register */
#define RTL_REGS_CSCR				0x74	/* Chip Status and Configuration Register. */
#define RTL_REGS_PARA_78			0x78
#define RTL_REGS_PARA_7c			0x7c	/* Magic transceiver parameter register. */
#define RTL_REGS_TPPOLL				0xd9	/* C+ transmit polling */
#define RTL_REGS_RXMSR				0xda	/* C+ max receive size*/
#define RTL_REGS_CPCR				0xe0	/* C+ command register*/
#define RTL_REGS_INTMITIR			0xe2	/* C+ interrupt mitigration */
#define RTL_REGS_RDSAR_0			0xe4	/* C+ receive descriptor start register low*/
#define RTL_REGS_RDSAR_1			0xe8	/* C+ receive descriptor start register high*/

#define RTL_REGS_ETTHR				0xec	/* C+ early transmit */



/* Rx Status Bits - From Rx Packet Header */

#define	RTL_RX_MULTICAST		0x8000
#define	RTL_RX_PHYSICAL			0x4000
#define	RTL_RX_BROADCAST		0x2000
#define	RTL_RX_BAD_SYMBOL		0x0020
#define	RTL_RX_RUNT				0x0010
#define	RTL_RX_TOO_LONG			0x0008
#define	RTL_RX_CRC_ERROR		0x0004
#define	RTL_RX_BAD_ALIGN		0x0002
#define	RTL_RX_STATUS_OK		0x0001

#define RTL_RX_UNFINISHED		0xfff0		/* DMA still in progress */


/* Tx Status Bits */
/* TSD0-3 - Offset 0010h - 001Fh - R/W */

#define	RTL_TX_HOST_OWNS		0x2000
#define	RTL_TX_UNDERRUN			0x4000
#define RTL_TX_STATUS_OK		0x8000
#define	RTL_TX_OUT_OF_WINDOW	0x20000000
#define	RTL_TX_ABORTED			0x40000000
#define	RTL_TX_CARRIER_LOST		0x80000000

/* Chip Command Bits */
/* Offset 0037h - R/W */

#define RTL_CMD_RESET			0x10
#define RTL_CMD_RX_ENB			0x08
#define RTL_CMD_TX_ENB			0x04
#define RTL_CMD_RX_BUF_EMPTY	0x01


/* Interrupt Mask & Status register bits */
/* Mask 	- Offset 003Ch-003Dh - R/W */