📄 init_se0111.c
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#include <reg54.h>
#include <stdio.h>
#include <math.h>
#include "se0111.h"
extern void delay();
extern unsigned char xdata lparray2m[3][21];
extern unsigned char xdata start_flg[4];
extern unsigned char xdata board_type[4][2]; //定义插盘类型数组，第一位表示槽号，第二位表示盘号
void se0111_reg_wr(unsigned char Haddr,unsigned char Laddr,unsigned char value,unsigned char slot){
switch(slot){
case 3 :
P1 = 0x40; break;
case 1 :
P1 = 0x20; break;
case 2 :
P1 = 0x60; break;
}
ADDRH = Haddr | 0x80;
ADDRL = Laddr;
SE0111_reg = value;
ADDRH = 0xFF;
ADDRL = 0xFF;
P1 = 0;
}
unsigned char se0111_reg_rd(unsigned char Haddr,unsigned char Laddr,unsigned char slot){
unsigned char xdata value;
switch(slot){
case 3 :
P1 = 0x40; break;
case 1 :
P1 = 0x20; break;
case 2 :
P1 = 0x60; break;
}
ADDRH = Haddr | 0x80;
ADDRL = Laddr;
value = SE0111_reg;
ADDRH = 0xFF;
ADDRL = 0xFF;
P1 = 0;
return(value);
}
void reset_se0111(unsigned char slot){
switch(slot){
case 3 :
P1 = 0x40; break;
case 1 :
P1 = 0x20; break;
case 2 :
P1 = 0x60; break;
}
ADDRH = 0;
delay();
ADDRH = 0x80; //reset se0111
P1 = 0;
}
void init_se0111(unsigned char slot){
unsigned char xdata i;
unsigned char xdata j;
reset_se0111(slot);
se0111_reg_wr(TEST_H,TEST_L,0x00,slot);
// se0111_reg_wr(Genctrl_reg1_H,Genctrl_reg1_L,0x40,slot);
// se0111_reg_wr(Genctrl_reg2_H,Genctrl_reg2_L,0x20,slot);
// se0111_reg_wr(Genctrl_reg3_H,Genctrl_reg3_L,0x00,slot);
// se0111_reg_wr(SE0111_RESET_H,SE0111_RESET_L,0x00,slot);
//修改begin
se0111_reg_wr(Genctrl_reg1_H_m,Genctrl_reg1_L_m,0x00,slot);//？？0401,原片0010地址对应0401（A路），0801（B路）
se0111_reg_wr(Genctrl_reg2_H_m,Genctrl_reg2_L_m,0x01,slot);//？？0400（A路）0800（B路）
se0111_reg_wr(Genctrl_reg3_H_m,Genctrl_reg3_L_m,0x04,slot);
se0111_reg_wr(SE0111_RESET_H_m,SE0111_RESET_L_m,0x00,slot);
/*
//对21路进行循环赋初始值
for (i = 0; i < 5; i++)
{
for (j = 0; j < 4; j++)
{
se0111_reg_wr(Ctrl_tx1_0H + (i * 8),Ctrl_tx1_0L + (j * 0x30),0x24,slot);
se0111_reg_wr(LeakRate_0H + (i * 8),LeakRate_0L + (j * 0x30),0x04,slot);
se0111_reg_wr(Ctrl_tx2_0H + (i * 8),Ctrl_tx2_0L + (j * 0x30),0x46,slot);
se0111_reg_wr(Ctrl_tx3_0H + (i * 8),Ctrl_tx3_0L + (j * 0x30),0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_0H + (i * 8),Tu12sele_rx_0L + (j * 0x30),0x01,slot);
// se0111_reg_wr(Tu12sele_tx_0H + (i * 8),Tu12sele_tx_0L + (j * 0x30),0x01,slot);
se0111_reg_wr(Ctrl_tx4_0H + (i * 8),Ctrl_tx4_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(Ctrl_tx5_0H + (i * 8),Ctrl_tx5_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(Ctrl_tx6_0H + (i * 8),Ctrl_tx6_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(V5_tx_0H + (i * 8),V5_tx_0L + (j * 0x30),0x02,slot);
se0111_reg_wr(K4_tx_0H + (i * 8),K4_tx_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(Obit_tx_0H + (i * 8),Obit_tx_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(V4_tx_0H + (i * 8),V4_tx_0L + (j * 0x30),0x00,slot);
se0111_reg_wr(LeakRate_0H + (i * 8),LeakRate_0L + (j * 0x30),0x10,slot);
}
}
//init No.20 timeslot 第21路不便于循环，单另初始化
se0111_reg_wr(Ctrl_tx1_20H,Ctrl_tx1_20L,0x24,slot);
se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_20H,Ctrl_tx2_20L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_20H,Ctrl_tx3_20L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
// se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
se0111_reg_wr(Ctrl_tx4_20H,Ctrl_tx4_20L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_20H,Ctrl_tx5_20L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_20H,Ctrl_tx6_20L,0x00,slot);
se0111_reg_wr(V5_tx_20H,V5_tx_20L,0x02,slot);
se0111_reg_wr(K4_tx_20H,K4_tx_20L,0x00,slot);
se0111_reg_wr(Obit_tx_20H,Obit_tx_20L,0x00,slot);
se0111_reg_wr(V4_tx_20H,V4_tx_20L,0x00,slot);
se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x10,slot);
*/
for (i = 0; i < 3; i++)
{
for (i = 0; i < 7; i++)
{
se0111_reg_wr(Ctrl_tx1_0H_m + i),Ctrl_tx1_0L_m + (j * 0x20),0x00,slot);
se0111_reg_wr(Ctrl_tx2_0H_m + i),Ctrl_tx2_0L_m + (j * 0x20),0x58,slot);
se0111_reg_wr(Ctrl_tx3_0H_m + i),Ctrl_tx3_0L_m + (j * 0x20),0xA0,slot);//？？新的022H对应原来（待定）
se0111_reg_wr(Ctrl_tx4_0H_m + i),Ctrl_tx4_0L_m + (j * 0x20),0x00,slot);//？？的004B和0050，且（待定）
//？？对应比特含义变化0050(A路B路)。
se0111_reg_wr(Ctrl_tx5_0H_m + i),Ctrl_tx5_0L_m + (j * 0x20),0x00,slot);//？？比特7含义变化（待定）（以及A路B路问题）
se0111_reg_wr(Ctrl_tx6_0H_m + i),Ctrl_tx6_0L_m + (j * 0x20),0x00,slot);//？？比特7含义变化（待定） （以及A路B路问题）
se0111_reg_wr(V5_tx_0H_m + i),V5_tx_0L_m + (j * 0x20),0x04,slot);//？？A路B路问题
se0111_reg_wr(K4_tx_0H_m + i),K4_tx_0L_m + (j * 0x20),0x00,slot);//??A路B路问题
se0111_reg_wr(Obit_tx_0H_m + i),Obit_tx_0L_m + (j * 0x20),0x00,slot);
se0111_reg_wr(V4_tx_0H_m + i),V4_tx_0L_m + (j * 0x20),0x00,slot);
}
}
//修改end
/******************************************************************
//init No.0 timeslot
se0111_reg_wr(Ctrl_tx1_0H,Ctrl_tx1_0L,0x14,slot);
se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_0H,Ctrl_tx2_0L,0x86,slot);
se0111_reg_wr(Ctrl_tx3_0H,Ctrl_tx3_0L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x01,slot);
// se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x01,slot);
se0111_reg_wr(Ctrl_tx4_0H,Ctrl_tx4_0L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_0H,Ctrl_tx5_0L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_0H,Ctrl_tx6_0L,0x00,slot);
se0111_reg_wr(V5_tx_0H,V5_tx_0L,0x02,slot);
se0111_reg_wr(K4_tx_0H,K4_tx_0L,0x00,slot);
se0111_reg_wr(Obit_tx_0H,Obit_tx_0L,0x00,slot);
se0111_reg_wr(V4_tx_0H,V4_tx_0L,0x00,slot);
se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x10,slot);
// for(i=0x0540;i<=0x057F;i++)
// se0111_reg_wr(i,0x00,slot);
//init No.1 timeslot
se0111_reg_wr(Ctrl_tx1_1H,Ctrl_tx1_1L,0x24,slot);
se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_1H,Ctrl_tx2_1L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_1H,Ctrl_tx3_1L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x02,slot);
// se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x02,slot);
se0111_reg_wr(Ctrl_tx4_1H,Ctrl_tx4_1L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_1H,Ctrl_tx5_1L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_1H,Ctrl_tx6_1L,0x00,slot);
se0111_reg_wr(V5_tx_1H,V5_tx_1L,0x02,slot);
se0111_reg_wr(K4_tx_1H,K4_tx_1L,0x00,slot);
se0111_reg_wr(Obit_tx_1H,Obit_tx_1L,0x00,slot);
se0111_reg_wr(V4_tx_1H,V4_tx_1L,0x00,slot);
se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x10,slot);
//init No.2 timeslot
se0111_reg_wr(Ctrl_tx1_2H,Ctrl_tx1_2L,0x24,slot);
se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_2H,Ctrl_tx2_2L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_2H,Ctrl_tx3_2L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x03,slot);
// se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x03,slot);
se0111_reg_wr(Ctrl_tx4_2H,Ctrl_tx4_2L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_2H,Ctrl_tx5_2L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_2H,Ctrl_tx6_2L,0x00,slot);
se0111_reg_wr(V5_tx_2H,V5_tx_2L,0x02,slot);
se0111_reg_wr(K4_tx_2H,K4_tx_2L,0x00,slot);
se0111_reg_wr(Obit_tx_2H,Obit_tx_2L,0x00,slot);
se0111_reg_wr(V4_tx_2H,V4_tx_2L,0x00,slot);
se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x10,slot);
//init No.3 timeslot
se0111_reg_wr(Ctrl_tx1_3H,Ctrl_tx1_3L,0x24,slot);
se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_3H,Ctrl_tx2_3L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_3H,Ctrl_tx3_3L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x04,slot);
// se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x04,slot);
se0111_reg_wr(Ctrl_tx4_3H,Ctrl_tx4_3L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_3H,Ctrl_tx5_3L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_3H,Ctrl_tx6_3L,0x00,slot);
se0111_reg_wr(V5_tx_3H,V5_tx_3L,0x02,slot);
se0111_reg_wr(K4_tx_3H,K4_tx_3L,0x00,slot);
se0111_reg_wr(Obit_tx_3H,Obit_tx_3L,0x00,slot);
se0111_reg_wr(V4_tx_3H,V4_tx_3L,0x00,slot);
se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x10,slot);
//init No.4 timeslot
se0111_reg_wr(Ctrl_tx1_4H,Ctrl_tx1_4L,0x24,slot);
se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_4H,Ctrl_tx2_4L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_4H,Ctrl_tx3_4L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x05,slot);
// se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x05,slot);
se0111_reg_wr(Ctrl_tx4_4H,Ctrl_tx4_4L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_4H,Ctrl_tx5_4L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_4H,Ctrl_tx6_4L,0x00,slot);
se0111_reg_wr(V5_tx_4H,V5_tx_4L,0x02,slot);
se0111_reg_wr(K4_tx_4H,K4_tx_4L,0x00,slot);
se0111_reg_wr(Obit_tx_4H,Obit_tx_4L,0x00,slot);
se0111_reg_wr(V4_tx_4H,V4_tx_4L,0x00,slot);
se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x10,slot);
//init No.5 timeslot
se0111_reg_wr(Ctrl_tx1_5H,Ctrl_tx1_5L,0x24,slot);
se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_5H,Ctrl_tx2_5L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_5H,Ctrl_tx3_5L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x06,slot);
// se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x06,slot);
se0111_reg_wr(Ctrl_tx4_5H,Ctrl_tx4_5L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_5H,Ctrl_tx5_5L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_5H,Ctrl_tx6_5L,0x00,slot);
se0111_reg_wr(V5_tx_5H,V5_tx_5L,0x02,slot);
se0111_reg_wr(K4_tx_5H,K4_tx_5L,0x00,slot);
se0111_reg_wr(Obit_tx_5H,Obit_tx_5L,0x00,slot);
se0111_reg_wr(V4_tx_5H,V4_tx_5L,0x00,slot);
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