📄 init_se0111.c.bak
字号:
se0111_reg_wr(Ctrl_tx2_17H,Ctrl_tx2_17L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_17H,Ctrl_tx3_17L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x12,slot);
// se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x12,slot);
se0111_reg_wr(Ctrl_tx4_17H,Ctrl_tx4_17L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_17H,Ctrl_tx5_17L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_17H,Ctrl_tx6_17L,0x00,slot);
se0111_reg_wr(V5_tx_17H,V5_tx_17L,0x02,slot);
se0111_reg_wr(K4_tx_17H,K4_tx_17L,0x00,slot);
se0111_reg_wr(Obit_tx_17H,Obit_tx_17L,0x00,slot);
se0111_reg_wr(V4_tx_17H,V4_tx_17L,0x00,slot);
se0111_reg_wr(LeakRate_17H,LeakRate_17L,0x10,slot);
//init No.18 timeslot
se0111_reg_wr(Ctrl_tx1_18H,Ctrl_tx1_18L,0x24,slot);
se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_18H,Ctrl_tx2_18L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_18H,Ctrl_tx3_18L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x13,slot);
// se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x13,slot);
se0111_reg_wr(Ctrl_tx4_18H,Ctrl_tx4_18L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_18H,Ctrl_tx5_18L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_18H,Ctrl_tx6_18L,0x00,slot);
se0111_reg_wr(V5_tx_18H,V5_tx_18L,0x02,slot);
se0111_reg_wr(K4_tx_18H,K4_tx_18L,0x00,slot);
se0111_reg_wr(Obit_tx_18H,Obit_tx_18L,0x00,slot);
se0111_reg_wr(V4_tx_18H,V4_tx_18L,0x00,slot);
se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x10,slot);
//init No.19 timeslot
se0111_reg_wr(Ctrl_tx1_19H,Ctrl_tx1_19L,0x24,slot);
se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_19H,Ctrl_tx2_19L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_19H,Ctrl_tx3_19L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x14,slot);
// se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x14,slot);
se0111_reg_wr(Ctrl_tx4_19H,Ctrl_tx4_19L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_19H,Ctrl_tx5_19L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_19H,Ctrl_tx6_19L,0x00,slot);
se0111_reg_wr(V5_tx_19H,V5_tx_19L,0x02,slot);
se0111_reg_wr(K4_tx_19H,K4_tx_19L,0x00,slot);
se0111_reg_wr(Obit_tx_19H,Obit_tx_19L,0x00,slot);
se0111_reg_wr(V4_tx_19H,V4_tx_19L,0x00,slot);
se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x10,slot);
//init No.20 timeslot
se0111_reg_wr(Ctrl_tx1_20H,Ctrl_tx1_20L,0x24,slot);
se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x04,slot);
se0111_reg_wr(Ctrl_tx2_20H,Ctrl_tx2_20L,0x46,slot);
se0111_reg_wr(Ctrl_tx3_20H,Ctrl_tx3_20L,0xA0,slot);
// se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
// se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
se0111_reg_wr(Ctrl_tx4_20H,Ctrl_tx4_20L,0x00,slot);
se0111_reg_wr(Ctrl_tx5_20H,Ctrl_tx5_20L,0x00,slot);
se0111_reg_wr(Ctrl_tx6_20H,Ctrl_tx6_20L,0x00,slot);
se0111_reg_wr(V5_tx_20H,V5_tx_20L,0x02,slot);
se0111_reg_wr(K4_tx_20H,K4_tx_20L,0x00,slot);
se0111_reg_wr(Obit_tx_20H,Obit_tx_20L,0x00,slot);
se0111_reg_wr(V4_tx_20H,V4_tx_20L,0x00,slot);
se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x10,slot);
/*
switch(slot){
case 1 :
se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x01,slot);
se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x01,slot);
se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x02,slot);
se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x02,slot);
se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x03,slot);
se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x03,slot);
se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x04,slot);
se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x04,slot);
se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x05,slot);
se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x05,slot);
se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x06,slot);
se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x06,slot);
se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x07,slot);
se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x07,slot);
se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x08,slot);
se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x08,slot);
se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x09,slot);
se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x09,slot);
se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x0A,slot);
se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x0A,slot);
se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x0B,slot);
se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x0B,slot);
se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x0C,slot);
se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x0C,slot);
se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x0D,slot);
se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x0D,slot);
se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x0E,slot);
se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x0E,slot);
se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x0F,slot);
se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x0F,slot);
se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x10,slot);
se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x10,slot);
se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x11,slot);
se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x11,slot);
se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x12,slot);
se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x12,slot);
se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x13,slot);
se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x13,slot);
se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x14,slot);
se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x14,slot);
se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
break;
case 2 :
se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x16,slot);
se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x16,slot);
se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x17,slot);
se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x17,slot);
se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x18,slot);
se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x18,slot);
se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x19,slot);
se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x19,slot);
se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x1A,slot);
se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x1A,slot);
se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x1B,slot);
se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x1B,slot);
se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x1C,slot);
se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x1C,slot);
se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x1D,slot);
se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x1D,slot);
se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x1E,slot);
se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x1E,slot);
se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x1F,slot);
se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x1F,slot);
se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x20,slot);
se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x20,slot);
se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x21,slot);
se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x21,slot);
se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x22,slot);
se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x22,slot);
se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x23,slot);
se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x23,slot);
se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x24,slot);
se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x24,slot);
se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x25,slot);
se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x25,slot);
se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x26,slot);
se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x26,slot);
se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x27,slot);
se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x27,slot);
se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x28,slot);
se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x28,slot);
se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x29,slot);
se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x29,slot);
se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x2A,slot);
se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x2A,slot);
break;
case 3 :
se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x2B,slot);
se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x2B,slot);
se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x2C,slot);
se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x2C,slot);
se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x2D,slot);
se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x2D,slot);
se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x2E,slot);
se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x2E,slot);
se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x2F,slot);
se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x2F,slot);
se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x30,slot);
se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x30,slot);
se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x31,slot);
se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x31,slot);
se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x32,slot);
se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x32,slot);
se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x33,slot);
se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x33,slot);
se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x34,slot);
se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x34,slot);
se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x35,slot);
se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x35,slot);
se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x36,slot);
se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x36,slot);
se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x37,slot);
se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x37,slot);
se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x38,slot);
se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x38,slot);
se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x39,slot);
se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x39,slot);
se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x3A,slot);
se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x3A,slot);
se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x3B,slot);
se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x3B,slot);
se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x3C,slot);
se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x3C,slot);
se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x3D,slot);
se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x3D,slot);
se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x3E,slot);
se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x3E,slot);
se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x3F,slot);
se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x3F,slot);
break;
}
*/
}
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