📄 init_se0111.ls1
字号:
00D0 120000 F 790 LCALL _se0111_reg_wr
791 ; se0111_reg_wr(Ctrl_tx5_7H,Ctrl_tx5_7L,0x00,slot);
792 ; SOURCE LINE # 246
00D3 850000 F 793 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00D6 7B00 794 MOV R3,#00H
00D8 7DE1 795 MOV R5,#0E1H
00DA 7F08 796 MOV R7,#08H
00DC 120000 F 797 LCALL _se0111_reg_wr
798 ; se0111_reg_wr(Ctrl_tx6_7H,Ctrl_tx6_7L,0x00,slot);
799 ; SOURCE LINE # 247
00DF 850000 F 800 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00E2 7B00 801 MOV R3,#00H
00E4 7DE2 802 MOV R5,#0E2H
00E6 7F08 803 MOV R7,#08H
00E8 120000 F 804 LCALL _se0111_reg_wr
805 ; se0111_reg_wr(V5_tx_7H,V5_tx_7L,0x02,slot);
806 ; SOURCE LINE # 248
00EB 850000 F 807 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00EE 7B02 808 MOV R3,#02H
00F0 7DE5 809 MOV R5,#0E5H
00F2 7F08 810 MOV R7,#08H
00F4 120000 F 811 LCALL _se0111_reg_wr
812 ; se0111_reg_wr(K4_tx_7H,K4_tx_7L,0x00,slot);
813 ; SOURCE LINE # 249
00F7 850000 F 814 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00FA 7B00 815 MOV R3,#00H
00FC 7DE8 816 MOV R5,#0E8H
00FE 7F08 817 MOV R7,#08H
0100 120000 F 818 LCALL _se0111_reg_wr
819 ; se0111_reg_wr(Obit_tx_7H,Obit_tx_7L,0x00,slot);
820 ; SOURCE LINE # 250
0103 850000 F 821 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
0106 7B00 822 MOV R3,#00H
0108 7DE9 823 MOV R5,#0E9H
010A 7F08 824 MOV R7,#08H
010C 120000 F 825 LCALL _se0111_reg_wr
826 ; se0111_reg_wr(V4_tx_7H,V4_tx_7L,0x00,slot);
827 ; SOURCE LINE # 251
010F 850000 F 828 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
0112 7B00 829 MOV R3,#00H
0114 7D91 830 MOV R5,#091H
0116 7F0E 831 MOV R7,#0EH
0118 120000 F 832 LCALL _se0111_reg_wr
833 ;
834 ; se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x10,slot);
835 ; SOURCE LINE # 253
011B 850000 F 836 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
011E 7B10 837 MOV R3,#010H
0120 7DD9 838 MOV R5,#0D9H
0122 7F08 839 MOV R7,#08H
0124 120000 F 840 LCALL _se0111_reg_wr
841 ; /*
842 ; //init No.8 timeslot
843 ; se0111_reg_wr(Ctrl_tx1_8H,Ctrl_tx1_8L,0x04,slot);
844 ; se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x04,slot);
845 ; se0111_reg_wr(Ctrl_tx2_8H,Ctrl_tx2_8L,0x46,slot);
846 ; se0111_reg_wr(Ctrl_tx3_8H,Ctrl_tx3_8L,0xA0,slot);
847 ; se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x09,slot);
848 ; se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x09,slot);
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 14
849 ; se0111_reg_wr(Ctrl_tx4_8H,Ctrl_tx4_8L,0x40,slot);
850 ; se0111_reg_wr(Ctrl_tx5_8H,Ctrl_tx5_8L,0x00,slot);
851 ; se0111_reg_wr(Ctrl_tx6_8H,Ctrl_tx6_8L,0x00,slot);
852 ; se0111_reg_wr(V5_tx_8H,V5_tx_8L,0x02,slot);
853 ; se0111_reg_wr(K4_tx_8H,K4_tx_8L,0x00,slot);
854 ; se0111_reg_wr(Obit_tx_8H,Obit_tx_8L,0x00,slot);
855 ; se0111_reg_wr(V4_tx_8H,V4_tx_8L,0x00,slot);
856 ;
857 ; se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x10,slot);
858 ;
859 ; //init No.9 timeslot
860 ; se0111_reg_wr(Ctrl_tx1_9H,Ctrl_tx1_9L,0x04,slot);
861 ; se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x04,slot);
862 ; se0111_reg_wr(Ctrl_tx2_9H,Ctrl_tx2_9L,0x46,slot);
863 ; se0111_reg_wr(Ctrl_tx3_9H,Ctrl_tx3_9L,0xA0,slot);
864 ; se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x0A,slot);
865 ; se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x0A,slot);
866 ; se0111_reg_wr(Ctrl_tx4_9H,Ctrl_tx4_9L,0x40,slot);
867 ; se0111_reg_wr(Ctrl_tx5_9H,Ctrl_tx5_9L,0x00,slot);
868 ; se0111_reg_wr(Ctrl_tx6_9H,Ctrl_tx6_9L,0x00,slot);
869 ; se0111_reg_wr(V5_tx_9H,V5_tx_9L,0x02,slot);
870 ; se0111_reg_wr(K4_tx_9H,K4_tx_9L,0x00,slot);
871 ; se0111_reg_wr(Obit_tx_9H,Obit_tx_9L,0x00,slot);
872 ; se0111_reg_wr(V4_tx_9H,V4_tx_9L,0x00,slot);
873 ;
874 ; se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x10,slot);
875 ;
876 ; //init No.10 timeslot
877 ; se0111_reg_wr(Ctrl_tx1_10H,Ctrl_tx1_10L,0x04,slot);
878 ; se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x04,slot);
879 ; se0111_reg_wr(Ctrl_tx2_10H,Ctrl_tx2_10L,0x46,slot);
880 ; se0111_reg_wr(Ctrl_tx3_10H,Ctrl_tx3_10L,0xA0,slot);
881 ; se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x0B,slot);
882 ; se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x0B,slot);
883 ; se0111_reg_wr(Ctrl_tx4_10H,Ctrl_tx4_10L,0x40,slot);
884 ; se0111_reg_wr(Ctrl_tx5_10H,Ctrl_tx5_10L,0x00,slot);
885 ; se0111_reg_wr(Ctrl_tx6_10H,Ctrl_tx6_10L,0x00,slot);
886 ; se0111_reg_wr(V5_tx_10H,V5_tx_10L,0x02,slot);
887 ; se0111_reg_wr(K4_tx_10H,K4_tx_10L,0x00,slot);
888 ; se0111_reg_wr(Obit_tx_10H,Obit_tx_10L,0x00,slot);
889 ; se0111_reg_wr(V4_tx_10H,V4_tx_10L,0x00,slot);
890 ;
891 ; se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x10,slot);
892 ;
893 ; //init No.11 timeslot
894 ; se0111_reg_wr(Ctrl_tx1_11H,Ctrl_tx1_11L,0x04,slot);
895 ; se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x04,slot);
896 ; se0111_reg_wr(Ctrl_tx2_11H,Ctrl_tx2_11L,0x46,slot);
897 ; se0111_reg_wr(Ctrl_tx3_11H,Ctrl_tx3_11L,0xA0,slot);
898 ; se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x0C,slot);
899 ; se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x0C,slot);
900 ; se0111_reg_wr(Ctrl_tx4_11H,Ctrl_tx4_11L,0x40,slot);
901 ; se0111_reg_wr(Ctrl_tx5_11H,Ctrl_tx5_11L,0x00,slot);
902 ; se0111_reg_wr(Ctrl_tx6_11H,Ctrl_tx6_11L,0x00,slot);
903 ; se0111_reg_wr(V5_tx_11H,V5_tx_11L,0x02,slot);
904 ; se0111_reg_wr(K4_tx_11H,K4_tx_11L,0x00,slot);
905 ; se0111_reg_wr(Obit_tx_11H,Obit_tx_11L,0x00,slot);
906 ; se0111_reg_wr(V4_tx_11H,V4_tx_11L,0x00,slot);
907 ;
908 ; se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x10,slot);
909 ;
910 ; //init No.12 timeslot
911 ; se0111_reg_wr(Ctrl_tx1_12H,Ctrl_tx1_12L,0x04,slot);
912 ; se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x04,slot);
913 ; se0111_reg_wr(Ctrl_tx2_12H,Ctrl_tx2_12L,0x46,slot);
914 ; se0111_reg_wr(Ctrl_tx3_12H,Ctrl_tx3_12L,0xA0,slot);
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 15
915 ; se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x0D,slot);
916 ; se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x0D,slot);
917 ; se0111_reg_wr(Ctrl_tx4_12H,Ctrl_tx4_12L,0x40,slot);
918 ; se0111_reg_wr(Ctrl_tx5_12H,Ctrl_tx5_12L,0x00,slot);
919 ; se0111_reg_wr(Ctrl_tx6_12H,Ctrl_tx6_12L,0x00,slot);
920 ; se0111_reg_wr(V5_tx_12H,V5_tx_12L,0x02,slot);
921 ; se0111_reg_wr(K4_tx_12H,K4_tx_12L,0x00,slot);
922 ; se0111_reg_wr(Obit_tx_12H,Obit_tx_12L,0x00,slot);
923 ; se0111_reg_wr(V4_tx_12H,V4_tx_12L,0x00,slot);
924 ;
925 ; se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x10,slot);
926 ;
927 ; //init No.13 timeslot
928 ; se0111_reg_wr(Ctrl_tx1_13H,Ctrl_tx1_13L,0x04,slot);
929 ; se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x04,slot);
930 ; se0111_reg_wr(Ctrl_tx2_13H,Ctrl_tx2_13L,0x46,slot);
931 ; se0111_reg_wr(Ctrl_tx3_13H,Ctrl_tx3_13L,0xA0,slot);
932 ; se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x0E,slot);
933 ; se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x0E,slot);
934 ; se0111_reg_wr(Ctrl_tx4_13H,Ctrl_tx4_13L,0x40,slot);
935 ; se0111_reg_wr(Ctrl_tx5_13H,Ctrl_tx5_13L,0x00,slot);
936 ; se0111_reg_wr(Ctrl_tx6_13H,Ctrl_tx6_13L,0x00,slot);
937 ; se0111_reg_wr(V5_tx_13H,V5_tx_13L,0x02,slot);
938 ; se0111_reg_wr(K4_tx_13H,K4_tx_13L,0x00,slot);
939 ; se0111_reg_wr(Obit_tx_13H,Obit_tx_13L,0x00,slot);
940 ; se0111_reg_wr(V4_tx_13H,V4_tx_13L,0x00,slot);
941 ;
942 ; se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x10,slot);
943 ;
944 ; //init No.14 timeslot
945 ; se0111_reg_wr(Ctrl_tx1_14H,Ctrl_tx1_14L,0x04,slot);
946 ; se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x04,slot);
947 ; se0111_reg_wr(Ctrl_tx2_14H,Ctrl_tx2_14L,0x46,slot);
948 ; se0111_reg_wr(Ctrl_tx3_14H,Ctrl_tx3_14L,0xA0,slot);
949 ; se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x0F,slot);
950 ; se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x0F,slot);
951 ; se0111_reg_wr(Ctrl_tx4_14H,Ctrl_tx4_14L,0x40,slot);
952 ; se0111_reg_wr(Ctrl_tx5_14H,Ctrl_tx5_14L,0x00,slot);
953 ; se0111_reg_wr(Ctrl_tx6_14H,Ctrl_tx6_14L,0x00,slot);
954 ; se0111_reg_wr(V5_tx_14H,V5_tx_14L,0x02,slot);
955 ; se0111_reg_wr(K4_tx_14H,K4_tx_14L,0x00,slot);
956 ; se0111_reg_wr(Obit_tx_14H,Obit_tx_14L,0x00,slot);
957 ; se0111_reg_wr(V4_tx_14H,V4_tx_14L,0x00,slot);
958 ;
959 ; se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x10,slot);
960 ;
961 ; //init No.15 timeslot
962 ; se0111_reg_wr(Ctrl_tx1_15H,Ctrl_tx1_15L,0x04,slot);
963 ; se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x04,slot);
964 ; se0111_reg_wr(Ctrl_tx2_15H,Ctrl_tx2_15L,0x46,slot);
965 ; se0111_reg_wr(Ctrl_tx3_15H,Ctrl_tx3_15L,0xA0,slot);
966 ; se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x10,slot);
967 ; se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x10,slot);
968 ; se0111_reg_wr(Ctrl_tx4_15H,Ctrl_tx4_15L,0x40,slot);
969 ; se0111_reg_wr(Ctrl_tx5_15H,Ctrl_tx5_15L,0x00,slot);
970 ; se0111_reg_wr(Ctrl_tx6_15H,Ctrl_tx6_15L,0x00,slot);
971 ; se0111_reg_wr(V5_tx_15H,V5_tx_15L,0x02,slot);
972 ; se0111_reg_wr(K4_tx_15H,K4_tx_15L,0x00,slot);
973 ; se0111_reg_wr(Obit_tx_15H,Obit_tx_15L,0x00,slot);
974 ; se0111_reg_wr(V4_tx_15H,V4_tx_15L,0x00,slot);
975 ;
976 ; se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x10,slot);
977 ;
978 ; //init No.16 timeslot
979 ; se0111_reg_wr(Ctrl_tx1_16H,Ctrl_tx1_16L,0x04,slot);
980 ; se0111_reg_wr(LeakRate_16H,LeakRate_16L,0x04,slot);
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 16
981 ; se0111_reg_wr(Ctrl_tx2_16H,Ctrl_tx2_16L,0x46,slot);
982 ; se0111_reg_wr(Ctrl_tx3_16H,Ctrl_tx3_16L,0xA0,slot);
983 ; se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x11,slot);
984 ; se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x11,slot);
985 ; ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -