📄 init_se0111.ls1
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0064 120000 F 590 LCALL _hextochar
591 ; hextochar(se0111_reg_rd(Genctrl_reg3_H,Genctrl_reg3_L,slot));
592 ; SOURCE LINE # 100
0067 AB00 F 593 MOV R3,slot?452
0069 7D13 594 MOV R5,#013H
006B 7F00 595 MOV R7,#00H
006D 120000 F 596 LCALL _se0111_reg_rd
0070 120000 F 597 LCALL _hextochar
598 ; hextochar(se0111_reg_rd(SE0111_RESET_H,SE0111_RESET_L,slot));
599 ; SOURCE LINE # 101
0073 AB00 F 600 MOV R3,slot?452
0075 7D15 601 MOV R5,#015H
0077 7F00 602 MOV R7,#00H
0079 120000 F 603 LCALL _se0111_reg_rd
007C 120000 F 604 LCALL _hextochar
605 ;
606 ; /*
607 ; //init No.0 timeslot
608 ; se0111_reg_wr(Ctrl_tx1_0H,Ctrl_tx1_0L,0x04,slot);
609 ; se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x04,slot);
610 ; se0111_reg_wr(Ctrl_tx2_0H,Ctrl_tx2_0L,0x46,slot);
611 ; se0111_reg_wr(Ctrl_tx3_0H,Ctrl_tx3_0L,0xA0,slot);
612 ; se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x01,slot);
613 ; se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x01,slot);
614 ; se0111_reg_wr(Ctrl_tx4_0H,Ctrl_tx4_0L,0x40,slot);
615 ; se0111_reg_wr(Ctrl_tx5_0H,Ctrl_tx5_0L,0x00,slot);
616 ; se0111_reg_wr(Ctrl_tx6_0H,Ctrl_tx6_0L,0x00,slot);
617 ; se0111_reg_wr(V5_tx_0H,V5_tx_0L,0x02,slot);
618 ; se0111_reg_wr(K4_tx_0H,K4_tx_0L,0x00,slot);
619 ; se0111_reg_wr(Obit_tx_0H,Obit_tx_0L,0x00,slot);
620 ; se0111_reg_wr(V4_tx_0H,V4_tx_0L,0x00,slot);
621 ; hextochar(se0111_reg_rd(Ctrl_tx1_0H,Ctrl_tx1_0L,slot));
622 ; hextochar(se0111_reg_rd(LeakRate_0H,LeakRate_0L,slot));
623 ; hextochar(se0111_reg_rd(Ctrl_tx2_0H,Ctrl_tx2_0L,slot));
624 ; hextochar(se0111_reg_rd(Ctrl_tx3_0H,Ctrl_tx3_0L,slot));
625 ; hextochar(se0111_reg_rd(Tu12sele_rx_0H,Tu12sele_rx_0L,slot));
626 ; hextochar(se0111_reg_rd(Tu12sele_tx_0H,Tu12sele_tx_0L,slot));
627 ; hextochar(se0111_reg_rd(Ctrl_tx4_0H,Ctrl_tx4_0L,slot));
628 ; hextochar(se0111_reg_rd(Ctrl_tx5_0H,Ctrl_tx5_0L,slot));
629 ; hextochar(se0111_reg_rd(Ctrl_tx6_0H,Ctrl_tx6_0L,slot));
630 ; hextochar(se0111_reg_rd(V5_tx_0H,V5_tx_0L,slot));
631 ; hextochar(se0111_reg_rd(K4_tx_0H,K4_tx_0L,slot));
632 ; hextochar(se0111_reg_rd(Obit_tx_0H,Obit_tx_0L,slot));
633 ; hextochar(se0111_reg_rd(V4_tx_0H,V4_tx_0L,slot));
634 ;
635 ; se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x10,slot);
636 ; // for(i=0x0540;i<=0x057F;i++)
637 ; // se0111_reg_wr(i,0x00,slot);
638 ;
639 ; //init No.1 timeslot
640 ; se0111_reg_wr(Ctrl_tx1_1H,Ctrl_tx1_1L,0x04,slot);
641 ; se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x04,slot);
642 ; se0111_reg_wr(Ctrl_tx2_1H,Ctrl_tx2_1L,0x46,slot);
643 ; se0111_reg_wr(Ctrl_tx3_1H,Ctrl_tx3_1L,0xA0,slot);
644 ; se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x02,slot);
645 ; se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x02,slot);
646 ; se0111_reg_wr(Ctrl_tx4_1H,Ctrl_tx4_1L,0x40,slot);
647 ; se0111_reg_wr(Ctrl_tx5_1H,Ctrl_tx5_1L,0x00,slot);
648 ; se0111_reg_wr(Ctrl_tx6_1H,Ctrl_tx6_1L,0x00,slot);
649 ; se0111_reg_wr(V5_tx_1H,V5_tx_1L,0x02,slot);
650 ; se0111_reg_wr(K4_tx_1H,K4_tx_1L,0x00,slot);
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 11
651 ; se0111_reg_wr(Obit_tx_1H,Obit_tx_1L,0x00,slot);
652 ; se0111_reg_wr(V4_tx_1H,V4_tx_1L,0x00,slot);
653 ;
654 ; se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x10,slot);
655 ;
656 ; //init No.2 timeslot
657 ; se0111_reg_wr(Ctrl_tx1_2H,Ctrl_tx1_2L,0x04,slot);
658 ; se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x04,slot);
659 ; se0111_reg_wr(Ctrl_tx2_2H,Ctrl_tx2_2L,0x46,slot);
660 ; se0111_reg_wr(Ctrl_tx3_2H,Ctrl_tx3_2L,0xA0,slot);
661 ; se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x03,slot);
662 ; se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x03,slot);
663 ; se0111_reg_wr(Ctrl_tx4_2H,Ctrl_tx4_2L,0x40,slot);
664 ; se0111_reg_wr(Ctrl_tx5_2H,Ctrl_tx5_2L,0x00,slot);
665 ; se0111_reg_wr(Ctrl_tx6_2H,Ctrl_tx6_2L,0x00,slot);
666 ; se0111_reg_wr(V5_tx_2H,V5_tx_2L,0x02,slot);
667 ; se0111_reg_wr(K4_tx_2H,K4_tx_2L,0x00,slot);
668 ; se0111_reg_wr(Obit_tx_2H,Obit_tx_2L,0x00,slot);
669 ; se0111_reg_wr(V4_tx_2H,V4_tx_2L,0x00,slot);
670 ;
671 ; se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x10,slot);
672 ;
673 ; //init No.3 timeslot
674 ; se0111_reg_wr(Ctrl_tx1_3H,Ctrl_tx1_3L,0x04,slot);
675 ; se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x04,slot);
676 ; se0111_reg_wr(Ctrl_tx2_3H,Ctrl_tx2_3L,0x46,slot);
677 ; se0111_reg_wr(Ctrl_tx3_3H,Ctrl_tx3_3L,0xA0,slot);
678 ; se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x04,slot);
679 ; se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x04,slot);
680 ; se0111_reg_wr(Ctrl_tx4_3H,Ctrl_tx4_3L,0x40,slot);
681 ; se0111_reg_wr(Ctrl_tx5_3H,Ctrl_tx5_3L,0x00,slot);
682 ; se0111_reg_wr(Ctrl_tx6_3H,Ctrl_tx6_3L,0x00,slot);
683 ; se0111_reg_wr(V5_tx_3H,V5_tx_3L,0x02,slot);
684 ; se0111_reg_wr(K4_tx_3H,K4_tx_3L,0x00,slot);
685 ; se0111_reg_wr(Obit_tx_3H,Obit_tx_3L,0x00,slot);
686 ; se0111_reg_wr(V4_tx_3H,V4_tx_3L,0x00,slot);
687 ;
688 ; se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x10,slot);
689 ;
690 ; //init No.4 timeslot
691 ; se0111_reg_wr(Ctrl_tx1_4H,Ctrl_tx1_4L,0x04,slot);
692 ; se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x04,slot);
693 ; se0111_reg_wr(Ctrl_tx2_4H,Ctrl_tx2_4L,0x46,slot);
694 ; se0111_reg_wr(Ctrl_tx3_4H,Ctrl_tx3_4L,0xA0,slot);
695 ; se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x05,slot);
696 ; se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x05,slot);
697 ; se0111_reg_wr(Ctrl_tx4_4H,Ctrl_tx4_4L,0x40,slot);
698 ; se0111_reg_wr(Ctrl_tx5_4H,Ctrl_tx5_4L,0x00,slot);
699 ; se0111_reg_wr(Ctrl_tx6_4H,Ctrl_tx6_4L,0x00,slot);
700 ; se0111_reg_wr(V5_tx_4H,V5_tx_4L,0x02,slot);
701 ; se0111_reg_wr(K4_tx_4H,K4_tx_4L,0x00,slot);
702 ; se0111_reg_wr(Obit_tx_4H,Obit_tx_4L,0x00,slot);
703 ; se0111_reg_wr(V4_tx_4H,V4_tx_4L,0x00,slot);
704 ;
705 ; se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x10,slot);
706 ;
707 ; //init No.5 timeslot
708 ; se0111_reg_wr(Ctrl_tx1_5H,Ctrl_tx1_5L,0x04,slot);
709 ; se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x04,slot);
710 ; se0111_reg_wr(Ctrl_tx2_5H,Ctrl_tx2_5L,0x46,slot);
711 ; se0111_reg_wr(Ctrl_tx3_5H,Ctrl_tx3_5L,0xA0,slot);
712 ; se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x06,slot);
713 ; se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x06,slot);
714 ; se0111_reg_wr(Ctrl_tx4_5H,Ctrl_tx4_5L,0x40,slot);
715 ; se0111_reg_wr(Ctrl_tx5_5H,Ctrl_tx5_5L,0x00,slot);
716 ; se0111_reg_wr(Ctrl_tx6_5H,Ctrl_tx6_5L,0x00,slot);
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 12
717 ; se0111_reg_wr(V5_tx_5H,V5_tx_5L,0x02,slot);
718 ; se0111_reg_wr(K4_tx_5H,K4_tx_5L,0x00,slot);
719 ; se0111_reg_wr(Obit_tx_5H,Obit_tx_5L,0x00,slot);
720 ; se0111_reg_wr(V4_tx_5H,V4_tx_5L,0x00,slot);
721 ;
722 ; se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x10,slot);
723 ;
724 ; //init No.6 timeslot
725 ; se0111_reg_wr(Ctrl_tx1_6H,Ctrl_tx1_6L,0x04,slot);
726 ; se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x04,slot);
727 ; se0111_reg_wr(Ctrl_tx2_6H,Ctrl_tx2_6L,0x46,slot);
728 ; se0111_reg_wr(Ctrl_tx3_6H,Ctrl_tx3_6L,0xA0,slot);
729 ; se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x07,slot);
730 ; se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x07,slot);
731 ; se0111_reg_wr(Ctrl_tx4_6H,Ctrl_tx4_6L,0x40,slot);
732 ; se0111_reg_wr(Ctrl_tx5_6H,Ctrl_tx5_6L,0x00,slot);
733 ; se0111_reg_wr(Ctrl_tx6_6H,Ctrl_tx6_6L,0x00,slot);
734 ; se0111_reg_wr(V5_tx_6H,V5_tx_6L,0x02,slot);
735 ; se0111_reg_wr(K4_tx_6H,K4_tx_6L,0x00,slot);
736 ; se0111_reg_wr(Obit_tx_6H,Obit_tx_6L,0x00,slot);
737 ; se0111_reg_wr(V4_tx_6H,V4_tx_6L,0x00,slot);
738 ;
739 ; se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x10,slot);
740 ; */
741 ; //init No.7 timeslot
742 ; se0111_reg_wr(Ctrl_tx1_7H,Ctrl_tx1_7L,0x04,slot);
743 ; SOURCE LINE # 239
007F 850000 F 744 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
0082 7B04 745 MOV R3,#04H
0084 7DD8 746 MOV R5,#0D8H
0086 7F08 747 MOV R7,#08H
0088 120000 F 748 LCALL _se0111_reg_wr
749 ; se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x04,slot);
750 ; SOURCE LINE # 240
008B 850000 F 751 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
008E 7B04 752 MOV R3,#04H
0090 7DD9 753 MOV R5,#0D9H
0092 7F08 754 MOV R7,#08H
0094 120000 F 755 LCALL _se0111_reg_wr
756 ; se0111_reg_wr(Ctrl_tx2_7H,Ctrl_tx2_7L,0x46,slot);
757 ; SOURCE LINE # 241
0097 850000 F 758 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
009A 7B46 759 MOV R3,#046H
009C 7DDA 760 MOV R5,#0DAH
009E 7F08 761 MOV R7,#08H
00A0 120000 F 762 LCALL _se0111_reg_wr
763 ; se0111_reg_wr(Ctrl_tx3_7H,Ctrl_tx3_7L,0xA0,slot);
764 ; SOURCE LINE # 242
00A3 850000 F 765 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00A6 7BA0 766 MOV R3,#0A0H
00A8 7DDB 767 MOV R5,#0DBH
00AA 7F08 768 MOV R7,#08H
00AC 120000 F 769 LCALL _se0111_reg_wr
770 ; se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x08,slot);
771 ; SOURCE LINE # 243
00AF 850000 F 772 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00B2 7B08 773 MOV R3,#08H
00B4 7DDC 774 MOV R5,#0DCH
00B6 7F08 775 MOV R7,#08H
00B8 120000 F 776 LCALL _se0111_reg_wr
777 ; se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x08,slot);
778 ; SOURCE LINE # 244
00BB 850000 F 779 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00BE 7B08 780 MOV R3,#08H
00C0 7DDD 781 MOV R5,#0DDH
00C2 7F08 782 MOV R7,#08H
A51 MACRO ASSEMBLER INIT_SE0111 01/27/2003 20:49:45 PAGE 13
00C4 120000 F 783 LCALL _se0111_reg_wr
784 ; se0111_reg_wr(Ctrl_tx4_7H,Ctrl_tx4_7L,0x40,slot);
785 ; SOURCE LINE # 245
00C7 850000 F 786 MOV ?_se0111_reg_wr?BYTE+03H,slot?452
00CA 7B40 787 MOV R3,#040H
00CC 7DE0 788 MOV R5,#0E0H
00CE 7F08 789 MOV R7,#08H
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