init_se0121.c

单片机程序代码,经过很详细的测试.呵呵,硬件相关.

#include <reg54.h>
#include <stdio.h>
#include <math.h>
#include "se0121.h"
#include "cmd_para_save.h"

extern void delay();

unsigned char se0121_reg_rd(unsigned char Laddr,unsigned char slot)
{
	unsigned char xdata value;
	
	switch(slot)
	{
		case 1:	P1 = 0x20;
				break;
		case 2: P1 = 0x60;
				break;
		case 3: P1 = 0x40;
				break;
		default:break;
	}
	ADDRL_SE0121 = Laddr | 0x80;
	value = SE0121_reg;

	ADDRL_SE0121 = 0xFF;
	P1 = 0;
	return(value);
}


void se0121_reg_wr(unsigned char Laddr,unsigned char value,unsigned char slot)
{
	switch(slot)
	{
		case 1:	P1 = 0x20;
				break;
		case 2: P1 = 0x60;
				break;
		case 3: P1 = 0x40;
				break;
		default:break;
	}
	ADDRL_SE0121 = Laddr | 0x80;
	SE0121_reg = value;
	
	ADDRL_SE0121 = 0xFF;
	P1 = 0;
}


void reset_se0121(unsigned char slot){
	switch(slot)
	{
		case 1: P1 = 0x20;
				break;
		case 2: P1 = 0x60;
				break;
		case 3: P1 = 0x40;
				break;
	}
	ADDRL_SE0121 = 0;
	delay();
	ADDRL_SE0121 = 0x80;		//reset se0111

	P1 = 0;
}


void init_se0121(unsigned char slot)
{
	reset_se0121(slot);

/*------------------SDH接口部分的初始化--------------------*/
	se0121_reg_wr(Eos_cortrol,0x0A,slot);

	se0121_reg_wr(Send_M1,0x00,slot);
	se0121_reg_wr(Send_M2,0x00,slot);
	se0121_reg_wr(Send_M3,0x00,slot);
	se0121_reg_wr(Send_M4,0x00,slot);
	se0121_reg_wr(Send_M5,0x00,slot);
	se0121_reg_wr(Recive_N1,0x00,slot);
	se0121_reg_wr(Recive_N2,0x00,slot);
	se0121_reg_wr(Recive_N3,0x00,slot);
	se0121_reg_wr(Recive_N4,0x00,slot);
	se0121_reg_wr(Recive_N5,0x00,slot);

	se0121_reg_wr(Eos_clock,0x40,slot);
	se0121_reg_wr(Eos_loop_AIS,0x00,slot);

/*--------------------以太网接口部分的初始化---------------*/
	se0121_reg_wr(CA_send,0x00,slot);
	se0121_reg_wr(CA_recv,0x00,slot);
	se0121_reg_wr(E_cortrol,0x24,slot);

	se0121_reg_wr(Timer_L,0xFF,slot);
	se0121_reg_wr(Timer_H,0xFF,slot);

	se0121_reg_wr(Imaddr_H,0x7F,slot);
	se0121_reg_wr(Imaddr_L,0xFF,slot);
	se0121_reg_wr(Omaddr_H,0x3F,slot);
	se0121_reg_wr(Omaddr_L,0xFF,slot);

	se0121_reg_wr(Set_SDRAM1,0x1C,slot);
	se0121_reg_wr(Ref_SDRAM,0x2A,slot);
	se0121_reg_wr(Ctl_sdram,0x20,slot);
	se0121_reg_wr(Slimit_H,0x03,slot);
	se0121_reg_wr(Slimit_L,0x0D,slot);
	se0121_reg_wr(S_wbl,0x00,slot);
	se0121_reg_wr(Set_SDRAM2,0x20,slot);

}