📄 init_se0111.src
字号:
; se0111_reg_wr(Ctrl_tx5_5H,Ctrl_tx5_5L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_5H,Ctrl_tx6_5L,0x00,slot);
; se0111_reg_wr(V5_tx_5H,V5_tx_5L,0x02,slot);
; se0111_reg_wr(K4_tx_5H,K4_tx_5L,0x00,slot);
; se0111_reg_wr(Obit_tx_5H,Obit_tx_5L,0x00,slot);
; se0111_reg_wr(V4_tx_5H,V4_tx_5L,0x00,slot);
;
; se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x10,slot);
;
; //init No.6 timeslot
; se0111_reg_wr(Ctrl_tx1_6H,Ctrl_tx1_6L,0x04,slot);
; se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_6H,Ctrl_tx2_6L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_6H,Ctrl_tx3_6L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x07,slot);
; se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x07,slot);
; se0111_reg_wr(Ctrl_tx4_6H,Ctrl_tx4_6L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_6H,Ctrl_tx5_6L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_6H,Ctrl_tx6_6L,0x00,slot);
; se0111_reg_wr(V5_tx_6H,V5_tx_6L,0x02,slot);
; se0111_reg_wr(K4_tx_6H,K4_tx_6L,0x00,slot);
; se0111_reg_wr(Obit_tx_6H,Obit_tx_6L,0x00,slot);
; se0111_reg_wr(V4_tx_6H,V4_tx_6L,0x00,slot);
;
; se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x10,slot);
; */
; //init No.7 timeslot
; se0111_reg_wr(Ctrl_tx1_7H,Ctrl_tx1_7L,0x04,slot);
; SOURCE LINE # 239
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#04H
MOV R5,#0D8H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x04,slot);
; SOURCE LINE # 240
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#04H
MOV R5,#0D9H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Ctrl_tx2_7H,Ctrl_tx2_7L,0x46,slot);
; SOURCE LINE # 241
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#046H
MOV R5,#0DAH
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Ctrl_tx3_7H,Ctrl_tx3_7L,0xA0,slot);
; SOURCE LINE # 242
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#0A0H
MOV R5,#0DBH
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x08,slot);
; SOURCE LINE # 243
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#08H
MOV R5,#0DCH
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x08,slot);
; SOURCE LINE # 244
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#08H
MOV R5,#0DDH
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Ctrl_tx4_7H,Ctrl_tx4_7L,0x40,slot);
; SOURCE LINE # 245
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#040H
MOV R5,#0E0H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Ctrl_tx5_7H,Ctrl_tx5_7L,0x00,slot);
; SOURCE LINE # 246
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#00H
MOV R5,#0E1H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Ctrl_tx6_7H,Ctrl_tx6_7L,0x00,slot);
; SOURCE LINE # 247
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#00H
MOV R5,#0E2H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(V5_tx_7H,V5_tx_7L,0x02,slot);
; SOURCE LINE # 248
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#02H
MOV R5,#0E5H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(K4_tx_7H,K4_tx_7L,0x00,slot);
; SOURCE LINE # 249
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#00H
MOV R5,#0E8H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(Obit_tx_7H,Obit_tx_7L,0x00,slot);
; SOURCE LINE # 250
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#00H
MOV R5,#0E9H
MOV R7,#08H
LCALL _se0111_reg_wr
; se0111_reg_wr(V4_tx_7H,V4_tx_7L,0x00,slot);
; SOURCE LINE # 251
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#00H
MOV R5,#091H
MOV R7,#0EH
LCALL _se0111_reg_wr
;
; se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x10,slot);
; SOURCE LINE # 253
MOV ?_se0111_reg_wr?BYTE+03H,slot?452
MOV R3,#010H
MOV R5,#0D9H
MOV R7,#08H
LCALL _se0111_reg_wr
; /*
; //init No.8 timeslot
; se0111_reg_wr(Ctrl_tx1_8H,Ctrl_tx1_8L,0x04,slot);
; se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_8H,Ctrl_tx2_8L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_8H,Ctrl_tx3_8L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x09,slot);
; se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x09,slot);
; se0111_reg_wr(Ctrl_tx4_8H,Ctrl_tx4_8L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_8H,Ctrl_tx5_8L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_8H,Ctrl_tx6_8L,0x00,slot);
; se0111_reg_wr(V5_tx_8H,V5_tx_8L,0x02,slot);
; se0111_reg_wr(K4_tx_8H,K4_tx_8L,0x00,slot);
; se0111_reg_wr(Obit_tx_8H,Obit_tx_8L,0x00,slot);
; se0111_reg_wr(V4_tx_8H,V4_tx_8L,0x00,slot);
;
; se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x10,slot);
;
; //init No.9 timeslot
; se0111_reg_wr(Ctrl_tx1_9H,Ctrl_tx1_9L,0x04,slot);
; se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_9H,Ctrl_tx2_9L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_9H,Ctrl_tx3_9L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x0A,slot);
; se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x0A,slot);
; se0111_reg_wr(Ctrl_tx4_9H,Ctrl_tx4_9L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_9H,Ctrl_tx5_9L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_9H,Ctrl_tx6_9L,0x00,slot);
; se0111_reg_wr(V5_tx_9H,V5_tx_9L,0x02,slot);
; se0111_reg_wr(K4_tx_9H,K4_tx_9L,0x00,slot);
; se0111_reg_wr(Obit_tx_9H,Obit_tx_9L,0x00,slot);
; se0111_reg_wr(V4_tx_9H,V4_tx_9L,0x00,slot);
;
; se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x10,slot);
;
; //init No.10 timeslot
; se0111_reg_wr(Ctrl_tx1_10H,Ctrl_tx1_10L,0x04,slot);
; se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_10H,Ctrl_tx2_10L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_10H,Ctrl_tx3_10L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x0B,slot);
; se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x0B,slot);
; se0111_reg_wr(Ctrl_tx4_10H,Ctrl_tx4_10L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_10H,Ctrl_tx5_10L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_10H,Ctrl_tx6_10L,0x00,slot);
; se0111_reg_wr(V5_tx_10H,V5_tx_10L,0x02,slot);
; se0111_reg_wr(K4_tx_10H,K4_tx_10L,0x00,slot);
; se0111_reg_wr(Obit_tx_10H,Obit_tx_10L,0x00,slot);
; se0111_reg_wr(V4_tx_10H,V4_tx_10L,0x00,slot);
;
; se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x10,slot);
;
; //init No.11 timeslot
; se0111_reg_wr(Ctrl_tx1_11H,Ctrl_tx1_11L,0x04,slot);
; se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_11H,Ctrl_tx2_11L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_11H,Ctrl_tx3_11L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x0C,slot);
; se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x0C,slot);
; se0111_reg_wr(Ctrl_tx4_11H,Ctrl_tx4_11L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_11H,Ctrl_tx5_11L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_11H,Ctrl_tx6_11L,0x00,slot);
; se0111_reg_wr(V5_tx_11H,V5_tx_11L,0x02,slot);
; se0111_reg_wr(K4_tx_11H,K4_tx_11L,0x00,slot);
; se0111_reg_wr(Obit_tx_11H,Obit_tx_11L,0x00,slot);
; se0111_reg_wr(V4_tx_11H,V4_tx_11L,0x00,slot);
;
; se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x10,slot);
;
; //init No.12 timeslot
; se0111_reg_wr(Ctrl_tx1_12H,Ctrl_tx1_12L,0x04,slot);
; se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_12H,Ctrl_tx2_12L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_12H,Ctrl_tx3_12L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x0D,slot);
; se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x0D,slot);
; se0111_reg_wr(Ctrl_tx4_12H,Ctrl_tx4_12L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_12H,Ctrl_tx5_12L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_12H,Ctrl_tx6_12L,0x00,slot);
; se0111_reg_wr(V5_tx_12H,V5_tx_12L,0x02,slot);
; se0111_reg_wr(K4_tx_12H,K4_tx_12L,0x00,slot);
; se0111_reg_wr(Obit_tx_12H,Obit_tx_12L,0x00,slot);
; se0111_reg_wr(V4_tx_12H,V4_tx_12L,0x00,slot);
;
; se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x10,slot);
;
; //init No.13 timeslot
; se0111_reg_wr(Ctrl_tx1_13H,Ctrl_tx1_13L,0x04,slot);
; se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_13H,Ctrl_tx2_13L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_13H,Ctrl_tx3_13L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x0E,slot);
; se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x0E,slot);
; se0111_reg_wr(Ctrl_tx4_13H,Ctrl_tx4_13L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_13H,Ctrl_tx5_13L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_13H,Ctrl_tx6_13L,0x00,slot);
; se0111_reg_wr(V5_tx_13H,V5_tx_13L,0x02,slot);
; se0111_reg_wr(K4_tx_13H,K4_tx_13L,0x00,slot);
; se0111_reg_wr(Obit_tx_13H,Obit_tx_13L,0x00,slot);
; se0111_reg_wr(V4_tx_13H,V4_tx_13L,0x00,slot);
;
; se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x10,slot);
;
; //init No.14 timeslot
; se0111_reg_wr(Ctrl_tx1_14H,Ctrl_tx1_14L,0x04,slot);
; se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_14H,Ctrl_tx2_14L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_14H,Ctrl_tx3_14L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x0F,slot);
; se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x0F,slot);
; se0111_reg_wr(Ctrl_tx4_14H,Ctrl_tx4_14L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_14H,Ctrl_tx5_14L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_14H,Ctrl_tx6_14L,0x00,slot);
; se0111_reg_wr(V5_tx_14H,V5_tx_14L,0x02,slot);
; se0111_reg_wr(K4_tx_14H,K4_tx_14L,0x00,slot);
; se0111_reg_wr(Obit_tx_14H,Obit_tx_14L,0x00,slot);
; se0111_reg_wr(V4_tx_14H,V4_tx_14L,0x00,slot);
;
; se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x10,slot);
;
; //init No.15 timeslot
; se0111_reg_wr(Ctrl_tx1_15H,Ctrl_tx1_15L,0x04,slot);
; se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_15H,Ctrl_tx2_15L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_15H,Ctrl_tx3_15L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x10,slot);
; se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x10,slot);
; se0111_reg_wr(Ctrl_tx4_15H,Ctrl_tx4_15L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_15H,Ctrl_tx5_15L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_15H,Ctrl_tx6_15L,0x00,slot);
; se0111_reg_wr(V5_tx_15H,V5_tx_15L,0x02,slot);
; se0111_reg_wr(K4_tx_15H,K4_tx_15L,0x00,slot);
; se0111_reg_wr(Obit_tx_15H,Obit_tx_15L,0x00,slot);
; se0111_reg_wr(V4_tx_15H,V4_tx_15L,0x00,slot);
;
; se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x10,slot);
;
; //init No.16 timeslot
; se0111_reg_wr(Ctrl_tx1_16H,Ctrl_tx1_16L,0x04,slot);
; se0111_reg_wr(LeakRate_16H,LeakRate_16L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_16H,Ctrl_tx2_16L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_16H,Ctrl_tx3_16L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x11,slot);
; se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x11,slot);
; se0111_reg_wr(Ctrl_tx4_16H,Ctrl_tx4_16L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_16H,Ctrl_tx5_16L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_16H,Ctrl_tx6_16L,0x00,slot);
; se0111_reg_wr(V5_tx_16H,V5_tx_16L,0x02,slot);
; se0111_reg_wr(K4_tx_16H,K4_tx_16L,0x00,slot);
; se0111_reg_wr(Obit_tx_16H,Obit_tx_16L,0x00,slot);
; se0111_reg_wr(V4_tx_16H,V4_tx_16L,0x00,slot);
;
; se0111_reg_wr(LeakRate_16H,LeakRate_16L,0x10,slot);
;
; //init No.17 timeslot
; se0111_reg_wr(Ctrl_tx1_17H,Ctrl_tx1_17L,0x04,slot);
; se0111_reg_wr(LeakRate_17H,LeakRate_17L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_17H,Ctrl_tx2_17L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_17H,Ctrl_tx3_17L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x12,slot);
; se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x12,slot);
; se0111_reg_wr(Ctrl_tx4_17H,Ctrl_tx4_17L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_17H,Ctrl_tx5_17L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_17H,Ctrl_tx6_17L,0x00,slot);
; se0111_reg_wr(V5_tx_17H,V5_tx_17L,0x02,slot);
; se0111_reg_wr(K4_tx_17H,K4_tx_17L,0x00,slot);
; se0111_reg_wr(Obit_tx_17H,Obit_tx_17L,0x00,slot);
; se0111_reg_wr(V4_tx_17H,V4_tx_17L,0x00,slot);
;
; se0111_reg_wr(LeakRate_17H,LeakRate_17L,0x10,slot);
;
; //init No.18 timeslot
; se0111_reg_wr(Ctrl_tx1_18H,Ctrl_tx1_18L,0x04,slot);
; se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_18H,Ctrl_tx2_18L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_18H,Ctrl_tx3_18L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x13,slot);
; se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x13,slot);
; se0111_reg_wr(Ctrl_tx4_18H,Ctrl_tx4_18L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_18H,Ctrl_tx5_18L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_18H,Ctrl_tx6_18L,0x00,slot);
; se0111_reg_wr(V5_tx_18H,V5_tx_18L,0x02,slot);
; se0111_reg_wr(K4_tx_18H,K4_tx_18L,0x00,slot);
; se0111_reg_wr(Obit_tx_18H,Obit_tx_18L,0x00,slot);
; se0111_reg_wr(V4_tx_18H,V4_tx_18L,0x00,slot);
;
; se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x10,slot);
;
; //init No.19 timeslot
; se0111_reg_wr(Ctrl_tx1_19H,Ctrl_tx1_19L,0x04,slot);
; se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_19H,Ctrl_tx2_19L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_19H,Ctrl_tx3_19L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x14,slot);
; se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x14,slot);
; se0111_reg_wr(Ctrl_tx4_19H,Ctrl_tx4_19L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_19H,Ctrl_tx5_19L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_19H,Ctrl_tx6_19L,0x00,slot);
; se0111_reg_wr(V5_tx_19H,V5_tx_19L,0x02,slot);
; se0111_reg_wr(K4_tx_19H,K4_tx_19L,0x00,slot);
; se0111_reg_wr(Obit_tx_19H,Obit_tx_19L,0x00,slot);
; se0111_reg_wr(V4_tx_19H,V4_tx_19L,0x00,slot);
;
; se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x10,slot);
;
; //init No.20 timeslot
; se0111_reg_wr(Ctrl_tx1_20H,Ctrl_tx1_20L,0x04,slot);
; se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x04,slot);
; se0111_reg_wr(Ctrl_tx2_20H,Ctrl_tx2_20L,0x46,slot);
; se0111_reg_wr(Ctrl_tx3_20H,Ctrl_tx3_20L,0xA0,slot);
; se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
; se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
; se0111_reg_wr(Ctrl_tx4_20H,Ctrl_tx4_20L,0x40,slot);
; se0111_reg_wr(Ctrl_tx5_20H,Ctrl_tx5_20L,0x00,slot);
; se0111_reg_wr(Ctrl_tx6_20H,Ctrl_tx6_20L,0x00,slot);
; se0111_reg_wr(V5_tx_20H,V5_tx_20L,0x02,slot);
; se0111_reg_wr(K4_tx_20H,K4_tx_20L,0x00,slot);
; se0111_reg_wr(Obit_tx_20H,Obit_tx_20L,0x00,slot);
; se0111_reg_wr(V4_tx_20H,V4_tx_20L,0x00,slot);
;
; se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x10,slot);
; */
; }
; SOURCE LINE # 476
?C0029:
RET
; END OF _init_se0111
END
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