📄 init_se0111.lst
字号:
330 1 se0111_reg_wr(Ctrl_tx2_12H,Ctrl_tx2_12L,0x46,slot);
331 1 se0111_reg_wr(Ctrl_tx3_12H,Ctrl_tx3_12L,0xA0,slot);
332 1 // se0111_reg_wr(Tu12sele_rx_12H,Tu12sele_rx_12L,0x0D,slot);
333 1 // se0111_reg_wr(Tu12sele_tx_12H,Tu12sele_tx_12L,0x0D,slot);
334 1 se0111_reg_wr(Ctrl_tx4_12H,Ctrl_tx4_12L,0x00,slot);
335 1 se0111_reg_wr(Ctrl_tx5_12H,Ctrl_tx5_12L,0x00,slot);
336 1 se0111_reg_wr(Ctrl_tx6_12H,Ctrl_tx6_12L,0x00,slot);
337 1 se0111_reg_wr(V5_tx_12H,V5_tx_12L,0x02,slot);
338 1 se0111_reg_wr(K4_tx_12H,K4_tx_12L,0x00,slot);
339 1 se0111_reg_wr(Obit_tx_12H,Obit_tx_12L,0x00,slot);
340 1 se0111_reg_wr(V4_tx_12H,V4_tx_12L,0x00,slot);
341 1
342 1 se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x10,slot);
343 1
344 1 //init No.13 timeslot
345 1 se0111_reg_wr(Ctrl_tx1_13H,Ctrl_tx1_13L,0x24,slot);
346 1 se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x04,slot);
347 1 se0111_reg_wr(Ctrl_tx2_13H,Ctrl_tx2_13L,0x46,slot);
348 1 se0111_reg_wr(Ctrl_tx3_13H,Ctrl_tx3_13L,0xA0,slot);
349 1 // se0111_reg_wr(Tu12sele_rx_13H,Tu12sele_rx_13L,0x0E,slot);
350 1 // se0111_reg_wr(Tu12sele_tx_13H,Tu12sele_tx_13L,0x0E,slot);
351 1 se0111_reg_wr(Ctrl_tx4_13H,Ctrl_tx4_13L,0x00,slot);
352 1 se0111_reg_wr(Ctrl_tx5_13H,Ctrl_tx5_13L,0x00,slot);
353 1 se0111_reg_wr(Ctrl_tx6_13H,Ctrl_tx6_13L,0x00,slot);
354 1 se0111_reg_wr(V5_tx_13H,V5_tx_13L,0x02,slot);
355 1 se0111_reg_wr(K4_tx_13H,K4_tx_13L,0x00,slot);
356 1 se0111_reg_wr(Obit_tx_13H,Obit_tx_13L,0x00,slot);
357 1 se0111_reg_wr(V4_tx_13H,V4_tx_13L,0x00,slot);
358 1
359 1 se0111_reg_wr(LeakRate_13H,LeakRate_13L,0x10,slot);
360 1
361 1 //init No.14 timeslot
362 1 se0111_reg_wr(Ctrl_tx1_14H,Ctrl_tx1_14L,0x24,slot);
363 1 se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x04,slot);
364 1 se0111_reg_wr(Ctrl_tx2_14H,Ctrl_tx2_14L,0x46,slot);
365 1 se0111_reg_wr(Ctrl_tx3_14H,Ctrl_tx3_14L,0xA0,slot);
C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 7
366 1 // se0111_reg_wr(Tu12sele_rx_14H,Tu12sele_rx_14L,0x0F,slot);
367 1 // se0111_reg_wr(Tu12sele_tx_14H,Tu12sele_tx_14L,0x0F,slot);
368 1 se0111_reg_wr(Ctrl_tx4_14H,Ctrl_tx4_14L,0x00,slot);
369 1 se0111_reg_wr(Ctrl_tx5_14H,Ctrl_tx5_14L,0x00,slot);
370 1 se0111_reg_wr(Ctrl_tx6_14H,Ctrl_tx6_14L,0x00,slot);
371 1 se0111_reg_wr(V5_tx_14H,V5_tx_14L,0x02,slot);
372 1 se0111_reg_wr(K4_tx_14H,K4_tx_14L,0x00,slot);
373 1 se0111_reg_wr(Obit_tx_14H,Obit_tx_14L,0x00,slot);
374 1 se0111_reg_wr(V4_tx_14H,V4_tx_14L,0x00,slot);
375 1
376 1 se0111_reg_wr(LeakRate_14H,LeakRate_14L,0x10,slot);
377 1
378 1 //init No.15 timeslot
379 1 se0111_reg_wr(Ctrl_tx1_15H,Ctrl_tx1_15L,0x24,slot);
380 1 se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x04,slot);
381 1 se0111_reg_wr(Ctrl_tx2_15H,Ctrl_tx2_15L,0x46,slot);
382 1 se0111_reg_wr(Ctrl_tx3_15H,Ctrl_tx3_15L,0xA0,slot);
383 1 // se0111_reg_wr(Tu12sele_rx_15H,Tu12sele_rx_15L,0x10,slot);
384 1 // se0111_reg_wr(Tu12sele_tx_15H,Tu12sele_tx_15L,0x10,slot);
385 1 se0111_reg_wr(Ctrl_tx4_15H,Ctrl_tx4_15L,0x00,slot);
386 1 se0111_reg_wr(Ctrl_tx5_15H,Ctrl_tx5_15L,0x00,slot);
387 1 se0111_reg_wr(Ctrl_tx6_15H,Ctrl_tx6_15L,0x00,slot);
388 1 se0111_reg_wr(V5_tx_15H,V5_tx_15L,0x02,slot);
389 1 se0111_reg_wr(K4_tx_15H,K4_tx_15L,0x00,slot);
390 1 se0111_reg_wr(Obit_tx_15H,Obit_tx_15L,0x00,slot);
391 1 se0111_reg_wr(V4_tx_15H,V4_tx_15L,0x00,slot);
392 1
393 1 se0111_reg_wr(LeakRate_15H,LeakRate_15L,0x10,slot);
394 1
395 1 //init No.16 timeslot
396 1 se0111_reg_wr(Ctrl_tx1_16H,Ctrl_tx1_16L,0x24,slot);
397 1 se0111_reg_wr(LeakRate_16H,LeakRate_16L,0x04,slot);
398 1 se0111_reg_wr(Ctrl_tx2_16H,Ctrl_tx2_16L,0x46,slot);
399 1 se0111_reg_wr(Ctrl_tx3_16H,Ctrl_tx3_16L,0xA0,slot);
400 1 // se0111_reg_wr(Tu12sele_rx_16H,Tu12sele_rx_16L,0x11,slot);
401 1 // se0111_reg_wr(Tu12sele_tx_16H,Tu12sele_tx_16L,0x11,slot);
402 1 se0111_reg_wr(Ctrl_tx4_16H,Ctrl_tx4_16L,0x00,slot);
403 1 se0111_reg_wr(Ctrl_tx5_16H,Ctrl_tx5_16L,0x00,slot);
404 1 se0111_reg_wr(Ctrl_tx6_16H,Ctrl_tx6_16L,0x00,slot);
405 1 se0111_reg_wr(V5_tx_16H,V5_tx_16L,0x02,slot);
406 1 se0111_reg_wr(K4_tx_16H,K4_tx_16L,0x00,slot);
407 1 se0111_reg_wr(Obit_tx_16H,Obit_tx_16L,0x00,slot);
408 1 se0111_reg_wr(V4_tx_16H,V4_tx_16L,0x00,slot);
409 1
410 1 se0111_reg_wr(LeakRate_16H,LeakRate_16L,0x10,slot);
411 1
412 1 //init No.17 timeslot
413 1 se0111_reg_wr(Ctrl_tx1_17H,Ctrl_tx1_17L,0x24,slot);
414 1 se0111_reg_wr(LeakRate_17H,LeakRate_17L,0x04,slot);
415 1 se0111_reg_wr(Ctrl_tx2_17H,Ctrl_tx2_17L,0x46,slot);
416 1 se0111_reg_wr(Ctrl_tx3_17H,Ctrl_tx3_17L,0xA0,slot);
417 1 // se0111_reg_wr(Tu12sele_rx_17H,Tu12sele_rx_17L,0x12,slot);
418 1 // se0111_reg_wr(Tu12sele_tx_17H,Tu12sele_tx_17L,0x12,slot);
419 1 se0111_reg_wr(Ctrl_tx4_17H,Ctrl_tx4_17L,0x00,slot);
420 1 se0111_reg_wr(Ctrl_tx5_17H,Ctrl_tx5_17L,0x00,slot);
421 1 se0111_reg_wr(Ctrl_tx6_17H,Ctrl_tx6_17L,0x00,slot);
422 1 se0111_reg_wr(V5_tx_17H,V5_tx_17L,0x02,slot);
423 1 se0111_reg_wr(K4_tx_17H,K4_tx_17L,0x00,slot);
424 1 se0111_reg_wr(Obit_tx_17H,Obit_tx_17L,0x00,slot);
425 1 se0111_reg_wr(V4_tx_17H,V4_tx_17L,0x00,slot);
426 1
427 1 se0111_reg_wr(LeakRate_17H,LeakRate_17L,0x10,slot);
C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 8
428 1
429 1 //init No.18 timeslot
430 1 se0111_reg_wr(Ctrl_tx1_18H,Ctrl_tx1_18L,0x24,slot);
431 1 se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x04,slot);
432 1 se0111_reg_wr(Ctrl_tx2_18H,Ctrl_tx2_18L,0x46,slot);
433 1 se0111_reg_wr(Ctrl_tx3_18H,Ctrl_tx3_18L,0xA0,slot);
434 1 // se0111_reg_wr(Tu12sele_rx_18H,Tu12sele_rx_18L,0x13,slot);
435 1 // se0111_reg_wr(Tu12sele_tx_18H,Tu12sele_tx_18L,0x13,slot);
436 1 se0111_reg_wr(Ctrl_tx4_18H,Ctrl_tx4_18L,0x00,slot);
437 1 se0111_reg_wr(Ctrl_tx5_18H,Ctrl_tx5_18L,0x00,slot);
438 1 se0111_reg_wr(Ctrl_tx6_18H,Ctrl_tx6_18L,0x00,slot);
439 1 se0111_reg_wr(V5_tx_18H,V5_tx_18L,0x02,slot);
440 1 se0111_reg_wr(K4_tx_18H,K4_tx_18L,0x00,slot);
441 1 se0111_reg_wr(Obit_tx_18H,Obit_tx_18L,0x00,slot);
442 1 se0111_reg_wr(V4_tx_18H,V4_tx_18L,0x00,slot);
443 1
444 1 se0111_reg_wr(LeakRate_18H,LeakRate_18L,0x10,slot);
445 1
446 1 //init No.19 timeslot
447 1 se0111_reg_wr(Ctrl_tx1_19H,Ctrl_tx1_19L,0x24,slot);
448 1 se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x04,slot);
449 1 se0111_reg_wr(Ctrl_tx2_19H,Ctrl_tx2_19L,0x46,slot);
450 1 se0111_reg_wr(Ctrl_tx3_19H,Ctrl_tx3_19L,0xA0,slot);
451 1 // se0111_reg_wr(Tu12sele_rx_19H,Tu12sele_rx_19L,0x14,slot);
452 1 // se0111_reg_wr(Tu12sele_tx_19H,Tu12sele_tx_19L,0x14,slot);
453 1 se0111_reg_wr(Ctrl_tx4_19H,Ctrl_tx4_19L,0x00,slot);
454 1 se0111_reg_wr(Ctrl_tx5_19H,Ctrl_tx5_19L,0x00,slot);
455 1 se0111_reg_wr(Ctrl_tx6_19H,Ctrl_tx6_19L,0x00,slot);
456 1 se0111_reg_wr(V5_tx_19H,V5_tx_19L,0x02,slot);
457 1 se0111_reg_wr(K4_tx_19H,K4_tx_19L,0x00,slot);
458 1 se0111_reg_wr(Obit_tx_19H,Obit_tx_19L,0x00,slot);
459 1 se0111_reg_wr(V4_tx_19H,V4_tx_19L,0x00,slot);
460 1
461 1 se0111_reg_wr(LeakRate_19H,LeakRate_19L,0x10,slot);
462 1
463 1 //init No.20 timeslot
464 1 se0111_reg_wr(Ctrl_tx1_20H,Ctrl_tx1_20L,0x24,slot);
465 1 se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x04,slot);
466 1 se0111_reg_wr(Ctrl_tx2_20H,Ctrl_tx2_20L,0x46,slot);
467 1 se0111_reg_wr(Ctrl_tx3_20H,Ctrl_tx3_20L,0xA0,slot);
468 1 // se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
469 1 // se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
470 1 se0111_reg_wr(Ctrl_tx4_20H,Ctrl_tx4_20L,0x00,slot);
471 1 se0111_reg_wr(Ctrl_tx5_20H,Ctrl_tx5_20L,0x00,slot);
472 1 se0111_reg_wr(Ctrl_tx6_20H,Ctrl_tx6_20L,0x00,slot);
473 1 se0111_reg_wr(V5_tx_20H,V5_tx_20L,0x02,slot);
474 1 se0111_reg_wr(K4_tx_20H,K4_tx_20L,0x00,slot);
475 1 se0111_reg_wr(Obit_tx_20H,Obit_tx_20L,0x00,slot);
476 1 se0111_reg_wr(V4_tx_20H,V4_tx_20L,0x00,slot);
477 1
478 1 se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x10,slot);
479 1 ***********************************************************************/
480 1 }
481
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 577 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 5
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 9
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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