init_se0111.lst

单片机程序代码,经过很详细的测试.呵呵,硬件相关.

 162   1      //      se0111_reg_wr(Tu12sele_tx_2H,Tu12sele_tx_2L,0x03,slot);
 163   1              se0111_reg_wr(Ctrl_tx4_2H,Ctrl_tx4_2L,0x00,slot);
 164   1              se0111_reg_wr(Ctrl_tx5_2H,Ctrl_tx5_2L,0x00,slot);
 165   1              se0111_reg_wr(Ctrl_tx6_2H,Ctrl_tx6_2L,0x00,slot);
 166   1              se0111_reg_wr(V5_tx_2H,V5_tx_2L,0x02,slot);
 167   1              se0111_reg_wr(K4_tx_2H,K4_tx_2L,0x00,slot);
 168   1              se0111_reg_wr(Obit_tx_2H,Obit_tx_2L,0x00,slot);
 169   1              se0111_reg_wr(V4_tx_2H,V4_tx_2L,0x00,slot);
 170   1      
 171   1              se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x10,slot);
 172   1      
 173   1      //init No.3 timeslot
 174   1              se0111_reg_wr(Ctrl_tx1_3H,Ctrl_tx1_3L,0x24,slot);
 175   1              se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x04,slot);
 176   1              se0111_reg_wr(Ctrl_tx2_3H,Ctrl_tx2_3L,0x46,slot);
 177   1              se0111_reg_wr(Ctrl_tx3_3H,Ctrl_tx3_3L,0xA0,slot);
 178   1      //      se0111_reg_wr(Tu12sele_rx_3H,Tu12sele_rx_3L,0x04,slot);
 179   1      //      se0111_reg_wr(Tu12sele_tx_3H,Tu12sele_tx_3L,0x04,slot);
C51 COMPILER V7.50   INIT_SE0111                                                           03/10/2006 16:35:16 PAGE 4   

 180   1              se0111_reg_wr(Ctrl_tx4_3H,Ctrl_tx4_3L,0x00,slot);
 181   1              se0111_reg_wr(Ctrl_tx5_3H,Ctrl_tx5_3L,0x00,slot);
 182   1              se0111_reg_wr(Ctrl_tx6_3H,Ctrl_tx6_3L,0x00,slot);
 183   1              se0111_reg_wr(V5_tx_3H,V5_tx_3L,0x02,slot);
 184   1              se0111_reg_wr(K4_tx_3H,K4_tx_3L,0x00,slot);
 185   1              se0111_reg_wr(Obit_tx_3H,Obit_tx_3L,0x00,slot);
 186   1              se0111_reg_wr(V4_tx_3H,V4_tx_3L,0x00,slot);
 187   1      
 188   1              se0111_reg_wr(LeakRate_3H,LeakRate_3L,0x10,slot);
 189   1      
 190   1      //init No.4 timeslot
 191   1              se0111_reg_wr(Ctrl_tx1_4H,Ctrl_tx1_4L,0x24,slot);
 192   1              se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x04,slot);
 193   1              se0111_reg_wr(Ctrl_tx2_4H,Ctrl_tx2_4L,0x46,slot);
 194   1              se0111_reg_wr(Ctrl_tx3_4H,Ctrl_tx3_4L,0xA0,slot);
 195   1      //      se0111_reg_wr(Tu12sele_rx_4H,Tu12sele_rx_4L,0x05,slot);
 196   1      //      se0111_reg_wr(Tu12sele_tx_4H,Tu12sele_tx_4L,0x05,slot);
 197   1              se0111_reg_wr(Ctrl_tx4_4H,Ctrl_tx4_4L,0x00,slot);
 198   1              se0111_reg_wr(Ctrl_tx5_4H,Ctrl_tx5_4L,0x00,slot);
 199   1              se0111_reg_wr(Ctrl_tx6_4H,Ctrl_tx6_4L,0x00,slot);
 200   1              se0111_reg_wr(V5_tx_4H,V5_tx_4L,0x02,slot);
 201   1              se0111_reg_wr(K4_tx_4H,K4_tx_4L,0x00,slot);
 202   1              se0111_reg_wr(Obit_tx_4H,Obit_tx_4L,0x00,slot);
 203   1              se0111_reg_wr(V4_tx_4H,V4_tx_4L,0x00,slot);
 204   1      
 205   1              se0111_reg_wr(LeakRate_4H,LeakRate_4L,0x10,slot);
 206   1      
 207   1      //init No.5 timeslot
 208   1              se0111_reg_wr(Ctrl_tx1_5H,Ctrl_tx1_5L,0x24,slot);
 209   1              se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x04,slot);
 210   1              se0111_reg_wr(Ctrl_tx2_5H,Ctrl_tx2_5L,0x46,slot);
 211   1              se0111_reg_wr(Ctrl_tx3_5H,Ctrl_tx3_5L,0xA0,slot);
 212   1      //      se0111_reg_wr(Tu12sele_rx_5H,Tu12sele_rx_5L,0x06,slot);
 213   1      //      se0111_reg_wr(Tu12sele_tx_5H,Tu12sele_tx_5L,0x06,slot);
 214   1              se0111_reg_wr(Ctrl_tx4_5H,Ctrl_tx4_5L,0x00,slot);
 215   1              se0111_reg_wr(Ctrl_tx5_5H,Ctrl_tx5_5L,0x00,slot);
 216   1              se0111_reg_wr(Ctrl_tx6_5H,Ctrl_tx6_5L,0x00,slot);
 217   1              se0111_reg_wr(V5_tx_5H,V5_tx_5L,0x02,slot);
 218   1              se0111_reg_wr(K4_tx_5H,K4_tx_5L,0x00,slot);
 219   1              se0111_reg_wr(Obit_tx_5H,Obit_tx_5L,0x00,slot);
 220   1              se0111_reg_wr(V4_tx_5H,V4_tx_5L,0x00,slot);
 221   1      
 222   1              se0111_reg_wr(LeakRate_5H,LeakRate_5L,0x10,slot);
 223   1      
 224   1      //init No.6 timeslot
 225   1              se0111_reg_wr(Ctrl_tx1_6H,Ctrl_tx1_6L,0x24,slot);
 226   1              se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x04,slot);
 227   1              se0111_reg_wr(Ctrl_tx2_6H,Ctrl_tx2_6L,0x46,slot);
 228   1              se0111_reg_wr(Ctrl_tx3_6H,Ctrl_tx3_6L,0xA0,slot);
 229   1      //      se0111_reg_wr(Tu12sele_rx_6H,Tu12sele_rx_6L,0x07,slot);
 230   1      //      se0111_reg_wr(Tu12sele_tx_6H,Tu12sele_tx_6L,0x07,slot);
 231   1              se0111_reg_wr(Ctrl_tx4_6H,Ctrl_tx4_6L,0x00,slot);
 232   1              se0111_reg_wr(Ctrl_tx5_6H,Ctrl_tx5_6L,0x00,slot);
 233   1              se0111_reg_wr(Ctrl_tx6_6H,Ctrl_tx6_6L,0x00,slot);
 234   1              se0111_reg_wr(V5_tx_6H,V5_tx_6L,0x02,slot);
 235   1              se0111_reg_wr(K4_tx_6H,K4_tx_6L,0x00,slot);
 236   1              se0111_reg_wr(Obit_tx_6H,Obit_tx_6L,0x00,slot);
 237   1              se0111_reg_wr(V4_tx_6H,V4_tx_6L,0x00,slot);
 238   1      
 239   1              se0111_reg_wr(LeakRate_6H,LeakRate_6L,0x10,slot);
 240   1      
 241   1      //init No.7 timeslot
C51 COMPILER V7.50   INIT_SE0111                                                           03/10/2006 16:35:16 PAGE 5   

 242   1              se0111_reg_wr(Ctrl_tx1_7H,Ctrl_tx1_7L,0x24,slot);
 243   1              se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x04,slot);
 244   1              se0111_reg_wr(Ctrl_tx2_7H,Ctrl_tx2_7L,0x46,slot);
 245   1              se0111_reg_wr(Ctrl_tx3_7H,Ctrl_tx3_7L,0xA0,slot);
 246   1      //      se0111_reg_wr(Tu12sele_rx_7H,Tu12sele_rx_7L,0x08,slot);
 247   1      //      se0111_reg_wr(Tu12sele_tx_7H,Tu12sele_tx_7L,0x08,slot);
 248   1              se0111_reg_wr(Ctrl_tx4_7H,Ctrl_tx4_7L,0x00,slot);
 249   1              se0111_reg_wr(Ctrl_tx5_7H,Ctrl_tx5_7L,0x00,slot);
 250   1              se0111_reg_wr(Ctrl_tx6_7H,Ctrl_tx6_7L,0x00,slot);
 251   1              se0111_reg_wr(V5_tx_7H,V5_tx_7L,0x02,slot);
 252   1              se0111_reg_wr(K4_tx_7H,K4_tx_7L,0x00,slot);
 253   1              se0111_reg_wr(Obit_tx_7H,Obit_tx_7L,0x00,slot);
 254   1              se0111_reg_wr(V4_tx_7H,V4_tx_7L,0x00,slot);
 255   1      
 256   1              se0111_reg_wr(LeakRate_7H,LeakRate_7L,0x10,slot);
 257   1      
 258   1      
 259   1      //init No.8 timeslot
 260   1              se0111_reg_wr(Ctrl_tx1_8H,Ctrl_tx1_8L,0x24,slot);
 261   1              se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x04,slot);
 262   1              se0111_reg_wr(Ctrl_tx2_8H,Ctrl_tx2_8L,0x46,slot);
 263   1              se0111_reg_wr(Ctrl_tx3_8H,Ctrl_tx3_8L,0xA0,slot);
 264   1      //      se0111_reg_wr(Tu12sele_rx_8H,Tu12sele_rx_8L,0x09,slot);
 265   1      //      se0111_reg_wr(Tu12sele_tx_8H,Tu12sele_tx_8L,0x09,slot);
 266   1              se0111_reg_wr(Ctrl_tx4_8H,Ctrl_tx4_8L,0x00,slot);
 267   1              se0111_reg_wr(Ctrl_tx5_8H,Ctrl_tx5_8L,0x00,slot);
 268   1              se0111_reg_wr(Ctrl_tx6_8H,Ctrl_tx6_8L,0x00,slot);
 269   1              se0111_reg_wr(V5_tx_8H,V5_tx_8L,0x02,slot);
 270   1              se0111_reg_wr(K4_tx_8H,K4_tx_8L,0x00,slot);
 271   1              se0111_reg_wr(Obit_tx_8H,Obit_tx_8L,0x00,slot);
 272   1              se0111_reg_wr(V4_tx_8H,V4_tx_8L,0x00,slot);
 273   1      
 274   1              se0111_reg_wr(LeakRate_8H,LeakRate_8L,0x10,slot);
 275   1      
 276   1      //init No.9  timeslot
 277   1              se0111_reg_wr(Ctrl_tx1_9H,Ctrl_tx1_9L,0x24,slot);
 278   1              se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x04,slot);
 279   1              se0111_reg_wr(Ctrl_tx2_9H,Ctrl_tx2_9L,0x46,slot);
 280   1              se0111_reg_wr(Ctrl_tx3_9H,Ctrl_tx3_9L,0xA0,slot);
 281   1      //      se0111_reg_wr(Tu12sele_rx_9H,Tu12sele_rx_9L,0x0A,slot);
 282   1      //      se0111_reg_wr(Tu12sele_tx_9H,Tu12sele_tx_9L,0x0A,slot);
 283   1              se0111_reg_wr(Ctrl_tx4_9H,Ctrl_tx4_9L,0x00,slot);
 284   1              se0111_reg_wr(Ctrl_tx5_9H,Ctrl_tx5_9L,0x00,slot);
 285   1              se0111_reg_wr(Ctrl_tx6_9H,Ctrl_tx6_9L,0x00,slot);
 286   1              se0111_reg_wr(V5_tx_9H,V5_tx_9L,0x02,slot);
 287   1              se0111_reg_wr(K4_tx_9H,K4_tx_9L,0x00,slot);
 288   1              se0111_reg_wr(Obit_tx_9H,Obit_tx_9L,0x00,slot);
 289   1              se0111_reg_wr(V4_tx_9H,V4_tx_9L,0x00,slot);
 290   1      
 291   1              se0111_reg_wr(LeakRate_9H,LeakRate_9L,0x10,slot);
 292   1      
 293   1      //init No.10  timeslot
 294   1              se0111_reg_wr(Ctrl_tx1_10H,Ctrl_tx1_10L,0x24,slot);
 295   1              se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x04,slot);
 296   1              se0111_reg_wr(Ctrl_tx2_10H,Ctrl_tx2_10L,0x46,slot);
 297   1              se0111_reg_wr(Ctrl_tx3_10H,Ctrl_tx3_10L,0xA0,slot);
 298   1      //      se0111_reg_wr(Tu12sele_rx_10H,Tu12sele_rx_10L,0x0B,slot);
 299   1      //      se0111_reg_wr(Tu12sele_tx_10H,Tu12sele_tx_10L,0x0B,slot);
 300   1              se0111_reg_wr(Ctrl_tx4_10H,Ctrl_tx4_10L,0x00,slot);
 301   1              se0111_reg_wr(Ctrl_tx5_10H,Ctrl_tx5_10L,0x00,slot);
 302   1              se0111_reg_wr(Ctrl_tx6_10H,Ctrl_tx6_10L,0x00,slot);
 303   1              se0111_reg_wr(V5_tx_10H,V5_tx_10L,0x02,slot);
C51 COMPILER V7.50   INIT_SE0111                                                           03/10/2006 16:35:16 PAGE 6   

 304   1              se0111_reg_wr(K4_tx_10H,K4_tx_10L,0x00,slot);
 305   1              se0111_reg_wr(Obit_tx_10H,Obit_tx_10L,0x00,slot);
 306   1              se0111_reg_wr(V4_tx_10H,V4_tx_10L,0x00,slot);
 307   1      
 308   1              se0111_reg_wr(LeakRate_10H,LeakRate_10L,0x10,slot);
 309   1      
 310   1      //init No.11 timeslot
 311   1              se0111_reg_wr(Ctrl_tx1_11H,Ctrl_tx1_11L,0x24,slot);
 312   1              se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x04,slot);
 313   1              se0111_reg_wr(Ctrl_tx2_11H,Ctrl_tx2_11L,0x46,slot);
 314   1              se0111_reg_wr(Ctrl_tx3_11H,Ctrl_tx3_11L,0xA0,slot);
 315   1      //      se0111_reg_wr(Tu12sele_rx_11H,Tu12sele_rx_11L,0x0C,slot);
 316   1      //      se0111_reg_wr(Tu12sele_tx_11H,Tu12sele_tx_11L,0x0C,slot);
 317   1              se0111_reg_wr(Ctrl_tx4_11H,Ctrl_tx4_11L,0x00,slot);
 318   1              se0111_reg_wr(Ctrl_tx5_11H,Ctrl_tx5_11L,0x00,slot);
 319   1              se0111_reg_wr(Ctrl_tx6_11H,Ctrl_tx6_11L,0x00,slot);
 320   1              se0111_reg_wr(V5_tx_11H,V5_tx_11L,0x02,slot);
 321   1              se0111_reg_wr(K4_tx_11H,K4_tx_11L,0x00,slot);
 322   1              se0111_reg_wr(Obit_tx_11H,Obit_tx_11L,0x00,slot);
 323   1              se0111_reg_wr(V4_tx_11H,V4_tx_11L,0x00,slot);
 324   1      
 325   1              se0111_reg_wr(LeakRate_11H,LeakRate_11L,0x10,slot);
 326   1      
 327   1      //init No.12 timeslot
 328   1              se0111_reg_wr(Ctrl_tx1_12H,Ctrl_tx1_12L,0x24,slot);
 329   1              se0111_reg_wr(LeakRate_12H,LeakRate_12L,0x04,slot);