📄 init_se0111.lst
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C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE INIT_SE0111
OBJECT MODULE PLACED IN init_se0111.OBJ
COMPILER INVOKED BY: e:\Keil\C51\BIN\C51.EXE init_se0111.c LARGE OPTIMIZE(9,SIZE) BROWSE NOAREGS DEBUG OBJECTEXTEND
line level source
1 #include <reg54.h>
2 #include <stdio.h>
3 #include <math.h>
4 #include "se0111.h"
5 extern void delay();
6
7 extern unsigned char xdata lparray2m[3][21];
8
9 extern unsigned char xdata start_flg[4];
10 extern unsigned char xdata board_type[4][2]; //定义插盘类型数组，第一位表示槽号，第二位表示盘号
11
12
13 void se0111_reg_wr(unsigned char Haddr,unsigned char Laddr,unsigned char value,unsigned char slot){
14 1 switch(slot){
15 2 case 3 :
16 2 P1 = 0x40; break;
17 2 case 1 :
18 2 P1 = 0x20; break;
19 2 case 2 :
20 2 P1 = 0x60; break;
21 2 }
22 1 ADDRH = Haddr | 0x80;
23 1 ADDRL = Laddr;
24 1 SE0111_reg = value;
25 1
26 1 ADDRH = 0xFF;
27 1 ADDRL = 0xFF;
28 1 P1 = 0;
29 1 }
30
31
32 unsigned char se0111_reg_rd(unsigned char Haddr,unsigned char Laddr,unsigned char slot){
33 1 unsigned char xdata value;
34 1 switch(slot){
35 2 case 3 :
36 2 P1 = 0x40; break;
37 2 case 1 :
38 2 P1 = 0x20; break;
39 2 case 2 :
40 2 P1 = 0x60; break;
41 2 }
42 1 ADDRH = Haddr | 0x80;
43 1 ADDRL = Laddr;
44 1 value = SE0111_reg;
45 1
46 1 ADDRH = 0xFF;
47 1 ADDRL = 0xFF;
48 1 P1 = 0;
49 1 return(value);
50 1 }
51
52 void reset_se0111(unsigned char slot){
53 1 switch(slot){
54 2 case 3 :
55 2 P1 = 0x40; break;
C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 2
56 2 case 1 :
57 2 P1 = 0x20; break;
58 2 case 2 :
59 2 P1 = 0x60; break;
60 2 }
61 1 ADDRH = 0;
62 1 delay();
63 1 ADDRH = 0x80; //reset se0111
64 1
65 1 P1 = 0;
66 1 }
67
68 void init_se0111(unsigned char slot){
69 1 unsigned char xdata i;
70 1 unsigned char xdata j;
71 1
72 1 reset_se0111(slot);
73 1
74 1 se0111_reg_wr(TEST_H,TEST_L,0x00,slot);
75 1 se0111_reg_wr(Genctrl_reg1_H_m,Genctrl_reg1_L_m,0x40,slot);
76 1 se0111_reg_wr(Genctrl_reg2_H_m,Genctrl_reg2_L_m,0x20,slot);
77 1 se0111_reg_wr(Genctrl_reg3_H_m,Genctrl_reg3_L_m,0x00,slot);
78 1 se0111_reg_wr(SE0111_RESET_H_m,SE0111_RESET_L_m,0x00,slot);
79 1
80 1 //对21路进行循环赋初始值
81 1 for (i = 0; i < 5; i++)
82 1 {
83 2 for (j = 0; j < 4; j++)
84 2 {
85 3 se0111_reg_wr(Ctrl_tx1_0H + (i * 8),Ctrl_tx1_0L + (j * 0x30),0x24,slot);
86 3 se0111_reg_wr(LeakRate_0H + (i * 8),LeakRate_0L + (j * 0x30),0x04,slot);
87 3 se0111_reg_wr(Ctrl_tx2_0H + (i * 8),Ctrl_tx2_0L + (j * 0x30),0x46,slot);
88 3 se0111_reg_wr(Ctrl_tx3_0H + (i * 8),Ctrl_tx3_0L + (j * 0x30),0xA0,slot);
89 3 // se0111_reg_wr(Tu12sele_rx_0H + (i * 8),Tu12sele_rx_0L + (j * 0x30),0x01,slot);
90 3 // se0111_reg_wr(Tu12sele_tx_0H + (i * 8),Tu12sele_tx_0L + (j * 0x30),0x01,slot);
91 3 se0111_reg_wr(Ctrl_tx4_0H + (i * 8),Ctrl_tx4_0L + (j * 0x30),0x00,slot);
92 3 se0111_reg_wr(Ctrl_tx5_0H + (i * 8),Ctrl_tx5_0L + (j * 0x30),0x00,slot);
93 3 se0111_reg_wr(Ctrl_tx6_0H + (i * 8),Ctrl_tx6_0L + (j * 0x30),0x00,slot);
94 3 se0111_reg_wr(V5_tx_0H + (i * 8),V5_tx_0L + (j * 0x30),0x02,slot);
95 3 se0111_reg_wr(K4_tx_0H + (i * 8),K4_tx_0L + (j * 0x30),0x00,slot);
96 3 se0111_reg_wr(Obit_tx_0H + (i * 8),Obit_tx_0L + (j * 0x30),0x00,slot);
97 3 se0111_reg_wr(V4_tx_0H + (i * 8),V4_tx_0L + (j * 0x30),0x00,slot);
98 3
99 3 se0111_reg_wr(LeakRate_0H + (i * 8),LeakRate_0L + (j * 0x30),0x10,slot);
100 3 }
101 2 }
102 1
103 1 //init No.20 timeslot 第21路不便于循环，单另初始化
104 1 se0111_reg_wr(Ctrl_tx1_20H,Ctrl_tx1_20L,0x24,slot);
105 1 se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x04,slot);
106 1 se0111_reg_wr(Ctrl_tx2_20H,Ctrl_tx2_20L,0x46,slot);
107 1 se0111_reg_wr(Ctrl_tx3_20H,Ctrl_tx3_20L,0xA0,slot);
108 1 // se0111_reg_wr(Tu12sele_rx_20H,Tu12sele_rx_20L,0x15,slot);
109 1 // se0111_reg_wr(Tu12sele_tx_20H,Tu12sele_tx_20L,0x15,slot);
110 1 se0111_reg_wr(Ctrl_tx4_20H,Ctrl_tx4_20L,0x00,slot);
111 1 se0111_reg_wr(Ctrl_tx5_20H,Ctrl_tx5_20L,0x00,slot);
112 1 se0111_reg_wr(Ctrl_tx6_20H,Ctrl_tx6_20L,0x00,slot);
113 1 se0111_reg_wr(V5_tx_20H,V5_tx_20L,0x02,slot);
114 1 se0111_reg_wr(K4_tx_20H,K4_tx_20L,0x00,slot);
115 1 se0111_reg_wr(Obit_tx_20H,Obit_tx_20L,0x00,slot);
116 1 se0111_reg_wr(V4_tx_20H,V4_tx_20L,0x00,slot);
117 1
C51 COMPILER V7.50 INIT_SE0111 03/10/2006 16:35:16 PAGE 3
118 1 se0111_reg_wr(LeakRate_20H,LeakRate_20L,0x10,slot);
119 1 /******************************************************************
120 1 //init No.0 timeslot
121 1 se0111_reg_wr(Ctrl_tx1_0H,Ctrl_tx1_0L,0x14,slot);
122 1 se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x04,slot);
123 1 se0111_reg_wr(Ctrl_tx2_0H,Ctrl_tx2_0L,0x86,slot);
124 1 se0111_reg_wr(Ctrl_tx3_0H,Ctrl_tx3_0L,0xA0,slot);
125 1 // se0111_reg_wr(Tu12sele_rx_0H,Tu12sele_rx_0L,0x01,slot);
126 1 // se0111_reg_wr(Tu12sele_tx_0H,Tu12sele_tx_0L,0x01,slot);
127 1 se0111_reg_wr(Ctrl_tx4_0H,Ctrl_tx4_0L,0x00,slot);
128 1 se0111_reg_wr(Ctrl_tx5_0H,Ctrl_tx5_0L,0x00,slot);
129 1 se0111_reg_wr(Ctrl_tx6_0H,Ctrl_tx6_0L,0x00,slot);
130 1 se0111_reg_wr(V5_tx_0H,V5_tx_0L,0x02,slot);
131 1 se0111_reg_wr(K4_tx_0H,K4_tx_0L,0x00,slot);
132 1 se0111_reg_wr(Obit_tx_0H,Obit_tx_0L,0x00,slot);
133 1 se0111_reg_wr(V4_tx_0H,V4_tx_0L,0x00,slot);
134 1
135 1 se0111_reg_wr(LeakRate_0H,LeakRate_0L,0x10,slot);
136 1 // for(i=0x0540;i<=0x057F;i++)
137 1 // se0111_reg_wr(i,0x00,slot);
138 1
139 1 //init No.1 timeslot
140 1 se0111_reg_wr(Ctrl_tx1_1H,Ctrl_tx1_1L,0x24,slot);
141 1 se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x04,slot);
142 1 se0111_reg_wr(Ctrl_tx2_1H,Ctrl_tx2_1L,0x46,slot);
143 1 se0111_reg_wr(Ctrl_tx3_1H,Ctrl_tx3_1L,0xA0,slot);
144 1 // se0111_reg_wr(Tu12sele_rx_1H,Tu12sele_rx_1L,0x02,slot);
145 1 // se0111_reg_wr(Tu12sele_tx_1H,Tu12sele_tx_1L,0x02,slot);
146 1 se0111_reg_wr(Ctrl_tx4_1H,Ctrl_tx4_1L,0x00,slot);
147 1 se0111_reg_wr(Ctrl_tx5_1H,Ctrl_tx5_1L,0x00,slot);
148 1 se0111_reg_wr(Ctrl_tx6_1H,Ctrl_tx6_1L,0x00,slot);
149 1 se0111_reg_wr(V5_tx_1H,V5_tx_1L,0x02,slot);
150 1 se0111_reg_wr(K4_tx_1H,K4_tx_1L,0x00,slot);
151 1 se0111_reg_wr(Obit_tx_1H,Obit_tx_1L,0x00,slot);
152 1 se0111_reg_wr(V4_tx_1H,V4_tx_1L,0x00,slot);
153 1
154 1 se0111_reg_wr(LeakRate_1H,LeakRate_1L,0x10,slot);
155 1
156 1 //init No.2 timeslot
157 1 se0111_reg_wr(Ctrl_tx1_2H,Ctrl_tx1_2L,0x24,slot);
158 1 se0111_reg_wr(LeakRate_2H,LeakRate_2L,0x04,slot);
159 1 se0111_reg_wr(Ctrl_tx2_2H,Ctrl_tx2_2L,0x46,slot);
160 1 se0111_reg_wr(Ctrl_tx3_2H,Ctrl_tx3_2L,0xA0,slot);
161 1 // se0111_reg_wr(Tu12sele_rx_2H,Tu12sele_rx_2L,0x03,slot);
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