📄 test.ls1
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0075 F0 409 MOVX @DPTR,A
410 ; // Config_ts0 = 0x31;
411 ;
412 ;
413 ; //init se0111
414 ; init_se0111(1);
415 ; SOURCE LINE # 134
0076 7F01 416 MOV R7,#01H
0078 120000 F 417 LCALL _init_se0111
418 ; init_se0111(2);
419 ; SOURCE LINE # 135
007B 7F02 420 MOV R7,#02H
007D 120000 F 421 LCALL _init_se0111
422 ; init_se0111(3);
423 ; SOURCE LINE # 136
0080 7F03 424 MOV R7,#03H
0082 120000 F 425 LCALL _init_se0111
426 ; // se0111_reg_wr(0x0050,0x40,2);
427 ;
428 ; // init ep1k50
429 ; init_1k50();
430 ; SOURCE LINE # 140
0085 120000 F 431 LCALL init_1k50
432 ;
433 ; // reset_se0111(2);
434 ; /*
435 ; //set mapper NRZ decoder and facility loopback
436 ; P1 = 0x20;
437 ; address = 0xA400;
438 ; *address = 0;
439 ; *address = 0x80; //reset
440 ; address = 0xA000;
441 ; *address = 0x4A;
A51 MACRO ASSEMBLER TEST 01/27/2003 20:49:48 PAGE 8
442 ; address = 0xA400;
443 ; *address = 0x80;
444 ; address = 0x9c00;
445 ; *address = 0x46; //write NRZ mode
446 ; */
447 ; // se0111_reg_wr(0x004A,0x46,2);
448 ;
449 ; /*
450 ; address = 0xA000;
451 ; *address = 0x50;
452 ; address = 0xA400;
453 ; *address = 0x80;
454 ; address = 0x9c00;
455 ; *address = 0x80; //write facility loopback
456 ; */
457 ;
458 ; // se0111_reg_wr(0x0050,0x80,2);
459 ;
460 ; /*
461 ; address = 0xA000;
462 ; *address = 0x00;
463 ; address = 0xA400;
464 ; *address = 0x80; //no effect reg
465 ;
466 ; P1 = 0;
467 ; */
468 ; P3_4 = 1;
469 ; SOURCE LINE # 177
0088 D2B4 470 SETB P3_4
008A 471 ?C0008:
472 ;
473 ; while (1) {
474 ; SOURCE LINE # 179
475 ; #if 1 // init ISD51 only when the uVision2 Debugger tries to connect
476 ; ISDcheck(); // initialize uVision2 Debugger and continue program r
un
477 ; SOURCE LINE # 181
008A 20AC10 478 JB ES,?C0010
008D 30980D 479 JNB RI,?C0010
0090 E599 480 MOV A,SBUF
0092 64A5 481 XRL A,#0A5H
0094 6004 482 JZ ?C0012
0096 C298 483 CLR RI
0098 8003 484 SJMP ?C0010
009A 485 ?C0012:
009A 120000 F 486 LCALL __isd_init
009D 487 ?C0013:
009D 488 ?C0011:
009D 489 ?C0010:
490 ; #endif
491 ; // P1=0x40;
492 ; P1=0x20;
493 ; SOURCE LINE # 184
009D 759020 494 MOV P1,#020H
495 ; test=se0111_reg_rd(0x08,0xd8,2);
496 ; SOURCE LINE # 185
00A0 7B02 497 MOV R3,#02H
00A2 7DD8 498 MOV R5,#0D8H
00A4 7F08 499 MOV R7,#08H
00A6 120000 F 500 LCALL _se0111_reg_rd
00A9 8F00 F 501 MOV test?141,R7
502 ; //#pragma asm
503 ; // mov acc,test?141
504 ; //#pragma endasm
505 ; test=se0111_reg_rd(0x08,0xd9,2);
506 ; SOURCE LINE # 189
A51 MACRO ASSEMBLER TEST 01/27/2003 20:49:48 PAGE 9
00AB 7B02 507 MOV R3,#02H
00AD 7DD9 508 MOV R5,#0D9H
00AF 7F08 509 MOV R7,#08H
00B1 120000 F 510 LCALL _se0111_reg_rd
00B4 8F00 F 511 MOV test?141,R7
512 ; //#pragma asm
513 ; // mov acc,test?141
514 ; //#pragma endasm
515 ; test=se0111_reg_rd(0x08,0xda,2);
516 ; SOURCE LINE # 193
00B6 7B02 517 MOV R3,#02H
00B8 7DDA 518 MOV R5,#0DAH
00BA 7F08 519 MOV R7,#08H
00BC 120000 F 520 LCALL _se0111_reg_rd
00BF 8F00 F 521 MOV test?141,R7
522 ; //#pragma asm
523 ; // mov acc,test?141
524 ; //#pragma endasm
525 ; test=se0111_reg_rd(0x08,0xdb,2);
526 ; SOURCE LINE # 197
00C1 7B02 527 MOV R3,#02H
00C3 7DDB 528 MOV R5,#0DBH
00C5 7F08 529 MOV R7,#08H
00C7 120000 F 530 LCALL _se0111_reg_rd
00CA 8F00 F 531 MOV test?141,R7
532 ; //#pragma asm
533 ; // mov acc,test?141
534 ; //#pragma endasm
535 ; test=se0111_reg_rd(0x08,0xdc,2);
536 ; SOURCE LINE # 201
00CC 7B02 537 MOV R3,#02H
00CE 7DDC 538 MOV R5,#0DCH
00D0 7F08 539 MOV R7,#08H
00D2 120000 F 540 LCALL _se0111_reg_rd
00D5 8F00 F 541 MOV test?141,R7
542 ; //#pragma asm
543 ; // mov acc,test?141
544 ; //#pragma endasm
545 ; test=se0111_reg_rd(0x08,0xdd,2);
546 ; SOURCE LINE # 205
00D7 7B02 547 MOV R3,#02H
00D9 7DDD 548 MOV R5,#0DDH
00DB 7F08 549 MOV R7,#08H
00DD 120000 F 550 LCALL _se0111_reg_rd
00E0 8F00 F 551 MOV test?141,R7
552 ; //#pragma asm
553 ; // mov acc,test?141
554 ; //#pragma endasm
555 ; test=se0111_reg_rd(0x08,0xe0,2);
556 ; SOURCE LINE # 209
00E2 7B02 557 MOV R3,#02H
00E4 7DE0 558 MOV R5,#0E0H
00E6 7F08 559 MOV R7,#08H
00E8 120000 F 560 LCALL _se0111_reg_rd
00EB 8F00 F 561 MOV test?141,R7
562 ; //#pragma asm
563 ; // mov acc,test?141
564 ; //#pragma endasm
565 ;
566 ;
567 ; P1=0;
568 ; SOURCE LINE # 215
00ED 759000 569 MOV P1,#00H
570 ; // P1=0x60;
571 ; // P1=0;
572 ; /* _nop_();
A51 MACRO ASSEMBLER TEST 01/27/2003 20:49:48 PAGE 10
573 ; _nop_();
574 ; _nop_();
575 ; _nop_();
576 ; _nop_();
577 ; _nop_();
578 ; _nop_();
579 ; _nop_();
580 ; Port_D = (Port_D) ^ 0x30;
581 ; P1 ^= 0x10;
582 ; _nop_();
583 ; _nop_();
584 ; _nop_();
585 ; #if 0 // you may use ISDbreak when ISD51 is started with ISDcheck or ISDw
ait
586 ; ISDbreak (); // hard coded stop (breakpoint)
587 ; #endif
588 ; delay();
589 ; _nop_();
590 ; _nop_();
591 ; _nop_(); */
592 ;
593 ; /* test = 0;
594 ; csx = 0;
595 ; csy = 0;
596 ; csz = 0;
597 ; //test microchip
598 ; P3_4 = 0;
599 ; P3_4 = 1;
600 ; //test ram
601 ; P3_4 = 0;
602 ;
603 ;
604 ; for(address=0x0000;address<=0x7fff;address++){ //clear ram
605 ; *address = 0x00;
606 ; }
607 ; for(address=0x0000;address<=0x7fff;address++){
608 ; *address = 0x55;
609 ; test = *address;
610 ; if (test != 0x55)
611 ; P3_4 = 1;
612 ; }
613 ;
614 ; //test cs7820 and r/w register
615 ; test = 0;
616 ; P3_4 = 0;
617 ; P1 = 0x50;
618 ; P1 = 0;
619 ; address = Mode_reg; //read
620 ; while(1){
621 ; test = *address;
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