📄 init_se0121.lst
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C51 COMPILER V7.50 INIT_SE0121 03/10/2006 16:35:53 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE INIT_SE0121
OBJECT MODULE PLACED IN init_se0121.OBJ
COMPILER INVOKED BY: e:\Keil\C51\BIN\C51.EXE init_se0121.c LARGE OPTIMIZE(9,SIZE) BROWSE NOAREGS DEBUG OBJECTEXTEND
line level source
1 #include <reg54.h>
2 #include <stdio.h>
3 #include <math.h>
4 #include "se0121.h"
5 #include "cmd_para_save.h"
6
7 extern void delay();
8
9 unsigned char se0121_reg_rd(unsigned char Laddr,unsigned char slot)
10 {
11 1 unsigned char xdata value;
12 1
13 1 switch(slot)
14 1 {
15 2 case 1: P1 = 0x20;
16 2 break;
17 2 case 2: P1 = 0x60;
18 2 break;
19 2 case 3: P1 = 0x40;
20 2 break;
21 2 default:break;
22 2 }
23 1 ADDRL_SE0121 = Laddr | 0x80;
24 1 value = SE0121_reg;
25 1
26 1 ADDRL_SE0121 = 0xFF;
27 1 P1 = 0;
28 1 return(value);
29 1 }
30
31
32 void se0121_reg_wr(unsigned char Laddr,unsigned char value,unsigned char slot)
33 {
34 1 switch(slot)
35 1 {
36 2 case 1: P1 = 0x20;
37 2 break;
38 2 case 2: P1 = 0x60;
39 2 break;
40 2 case 3: P1 = 0x40;
41 2 break;
42 2 default:break;
43 2 }
44 1 ADDRL_SE0121 = Laddr | 0x80;
45 1 SE0121_reg = value;
46 1
47 1 ADDRL_SE0121 = 0xFF;
48 1 P1 = 0;
49 1 }
50
51
52 void reset_se0121(unsigned char slot){
53 1 switch(slot)
54 1 {
55 2 case 1: P1 = 0x20;
C51 COMPILER V7.50 INIT_SE0121 03/10/2006 16:35:53 PAGE 2
56 2 break;
57 2 case 2: P1 = 0x60;
58 2 break;
59 2 case 3: P1 = 0x40;
60 2 break;
61 2 }
62 1 ADDRL_SE0121 = 0;
63 1 delay();
64 1 ADDRL_SE0121 = 0x80; //reset se0111
65 1
66 1 P1 = 0;
67 1 }
68
69
70 void init_se0121(unsigned char slot)
71 {
72 1 reset_se0121(slot);
73 1
74 1 /*------------------SDH接口部分的初始化--------------------*/
75 1 se0121_reg_wr(Eos_cortrol,0x0A,slot);
76 1
77 1 se0121_reg_wr(Send_M1,0x00,slot);
78 1 se0121_reg_wr(Send_M2,0x00,slot);
79 1 se0121_reg_wr(Send_M3,0x00,slot);
80 1 se0121_reg_wr(Send_M4,0x00,slot);
81 1 se0121_reg_wr(Send_M5,0x00,slot);
82 1 se0121_reg_wr(Recive_N1,0x00,slot);
83 1 se0121_reg_wr(Recive_N2,0x00,slot);
84 1 se0121_reg_wr(Recive_N3,0x00,slot);
85 1 se0121_reg_wr(Recive_N4,0x00,slot);
86 1 se0121_reg_wr(Recive_N5,0x00,slot);
87 1
88 1 se0121_reg_wr(Eos_clock,0x40,slot);
89 1 se0121_reg_wr(Eos_loop_AIS,0x00,slot);
90 1
91 1 /*--------------------以太网接口部分的初始化---------------*/
92 1 se0121_reg_wr(CA_send,0x00,slot);
93 1 se0121_reg_wr(CA_recv,0x00,slot);
94 1 se0121_reg_wr(E_cortrol,0x24,slot);
95 1
96 1 se0121_reg_wr(Timer_L,0xFF,slot);
97 1 se0121_reg_wr(Timer_H,0xFF,slot);
98 1
99 1 se0121_reg_wr(Imaddr_H,0x7F,slot);
100 1 se0121_reg_wr(Imaddr_L,0xFF,slot);
101 1 se0121_reg_wr(Omaddr_H,0x3F,slot);
102 1 se0121_reg_wr(Omaddr_L,0xFF,slot);
103 1
104 1 se0121_reg_wr(Set_SDRAM1,0x1C,slot);
105 1 se0121_reg_wr(Ref_SDRAM,0x2A,slot);
106 1 se0121_reg_wr(Ctl_sdram,0x20,slot);
107 1 se0121_reg_wr(Slimit_H,0x03,slot);
108 1 se0121_reg_wr(Slimit_L,0x0D,slot);
109 1 se0121_reg_wr(S_wbl,0x00,slot);
110 1 se0121_reg_wr(Set_SDRAM2,0x20,slot);
111 1
112 1 }
113
114
115
C51 COMPILER V7.50 INIT_SE0121 03/10/2006 16:35:53 PAGE 3
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 291 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 1
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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