📄 counter24b.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER24B IS
PORT(FIN: IN STD_LOGIC;
CLR: IN STD_LOGIC;
ENABL: IN STD_LOGIC;
COUT:OUT STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END COUNTER24B;
ARCHITECTURE behav OF COUNTER24B IS
SIGNAL Q0,Q1,Q2,Q3,Q4,Q5: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C0,C1,C2,C3,C4,C5: STD_LOGIC;
BEGIN
PROCESS(FIN,ENABL,CLR)
BEGIN
IF CLR='1' THEN Q0<=(OTHERS=>'0');Q1<=(OTHERS=>'0');Q2<=(OTHERS=>'0');Q3<=(OTHERS=>'0');Q4<=(OTHERS=>'0');Q5<=(OTHERS=>'0');C5<='0';
ELSIF FIN'EVENT AND FIN='1' THEN
IF ENABL='1' THEN
IF Q0<"1001" THEN Q0<=Q0+1;
elsif Q0>"1001" THEN Q0<=(OTHERS=>'0');
elsif
Q0="1001" THEN C0<='1';Q0<=(OTHERS=>'0');
IF Q1<"1001" THEN Q1<=Q1+1;
elsif Q1>"1001" THEN Q1<=(OTHERS=>'0');
elsif Q1="1001" THEN C1<='1';Q1<=(OTHERS=>'0');
IF Q2<"1001" THEN Q2<=Q2+1;
elsif Q2>"1001" THEN Q2<=(OTHERS=>'0');
elsif Q2="1001" THEN C2<='1';Q2<=(OTHERS=>'0');
IF Q3<"1001" THEN Q3<=Q3+1;
elsif Q3>"1001" THEN Q3<=(OTHERS=>'0');
elsif Q3="1001" THEN C3<='1';Q3<=(OTHERS=>'0');
IF Q4<"1001" THEN Q4<=Q4+1;
elsif Q4>"1001" THEN Q4<=(OTHERS=>'0');
elsif Q4="1001" THEN C4<='1';Q4<=(OTHERS=>'0');
IF Q5<"1001" THEN Q5<=Q5+1;
elsif Q5>="1001" THEN C5<='1';Q5<=(OTHERS=>'0');
ELSE C5<='0';
END IF;
ELSE C4<='0';
END IF;
ELSE C3<='0';
END IF;
ELSE C2<='0';
END IF;
ELSE C1<='0';
END IF;
ELSE C0<='0';
END IF;
END IF;
END IF;
END PROCESS;
COUT<=C5;
DOUT<=Q5&Q4&Q3&Q2&Q1&Q0;
END behav;
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