freqtest.rpt

可编程逻辑设计的程序！24位十进制频率计！可使ＥＤＡ实验年箱测量指定频率！

-- Node name is '|COUNTER24B:U3|~2341~1' 
-- Equation name is '_LC5_F12', type is buried 
-- synthesized logic cell 
_LC5_F12 = LCELL( _EQ069);
  _EQ069 =  _LC2_F4 & !_LC2_F12
         #  _LC4_F12;

-- Node name is '|COUNTER24B:U3|~2347~1' 
-- Equation name is '_LC4_F12', type is buried 
-- synthesized logic cell 
_LC4_F12 = LCELL( _EQ070);
  _EQ070 = !_LC3_F12
         # !_LC8_F7;

-- Node name is '|COUNTER24B:U3|~2353~1' 
-- Equation name is '_LC8_F5', type is buried 
-- synthesized logic cell 
_LC8_F5  = LCELL( _EQ071);
  _EQ071 =  _LC1_F12 & !_LC7_F5
         #  _LC1_F12 & !_LC6_F7
         #  _LC5_F7;

-- Node name is '|COUNTER24B:U3|~2365~1' 
-- Equation name is '_LC2_F7', type is buried 
-- synthesized logic cell 
_LC2_F7  = LCELL( _EQ072);
  _EQ072 =  _LC1_F12 & !_LC8_F7
         #  _LC5_F7;

-- Node name is '|COUNTER24B:U3|~2371~1' 
-- Equation name is '_LC5_F7', type is buried 
-- synthesized logic cell 
_LC5_F7  = LCELL( _EQ073);
  _EQ073 = !_LC7_F20
         # !_LC1_F30;

-- Node name is '|COUNTER24B:U3|~2377~1' 
-- Equation name is '_LC8_F20', type is buried 
-- synthesized logic cell 
_LC8_F20 = LCELL( _EQ074);
  _EQ074 = !_LC3_F20 &  _LC5_F20
         # !_LC1_F27 &  _LC5_F20
         #  _LC8_F30;

-- Node name is '|COUNTER24B:U3|~2389~1' 
-- Equation name is '_LC4_F30', type is buried 
-- synthesized logic cell 
_LC4_F30 = LCELL( _EQ075);
  _EQ075 = !_LC1_F30 &  _LC5_F20
         #  _LC8_F30;

-- Node name is '|COUNTER24B:U3|~2395~1' 
-- Equation name is '_LC8_F30', type is buried 
-- synthesized logic cell 
_LC8_F30 = LCELL( _EQ076);
  _EQ076 = !_LC6_F30
         # !_LC6_F26;

-- Node name is '|COUNTER24B:U3|~2401~1' 
-- Equation name is '_LC8_F26', type is buried 
-- synthesized logic cell 
_LC8_F26 = LCELL( _EQ077);
  _EQ077 = !_LC1_F26 &  _LC3_F30
         #  _LC3_F30 & !_LC6_F35
         #  _LC4_F26;

-- Node name is '|COUNTER24B:U3|~2413~1' 
-- Equation name is '_LC5_F26', type is buried 
-- synthesized logic cell 
_LC5_F26 = LCELL( _EQ078);
  _EQ078 =  _LC3_F30 & !_LC6_F26
         #  _LC4_F26;

-- Node name is '|COUNTER24B:U3|~2419~1' 
-- Equation name is '_LC4_F26', type is buried 
-- synthesized logic cell 
_LC4_F26 = LCELL( _EQ079);
  _EQ079 = !_LC4_F25
         # !_LC1_F25;

-- Node name is '|FTCTRL:U1|:5' = '|FTCTRL:U1|Div2CLK' 
-- Equation name is '_LC3_F35', type is buried 
_LC3_F35 = DFFE(!_LC3_F35, GLOBAL( CLK1HZ),  VCC,  VCC,  VCC);

-- Node name is '|FTCTRL:U1|:36' 
-- Equation name is '_LC7_F1', type is buried 
!_LC7_F1 = _LC7_F1~NOT;
_LC7_F1~NOT = LCELL( _EQ080);
  _EQ080 =  _LC3_F35
         #  CLK1HZ;

-- Node name is '|REG24B:U2|:26' 
-- Equation name is '_LC4_E20', type is buried 
_LC4_E20 = DFFE( _LC3_E33, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:28' 
-- Equation name is '_LC8_E33', type is buried 
_LC8_E33 = DFFE( _LC1_E33, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:30' 
-- Equation name is '_LC1_E20', type is buried 
_LC1_E20 = DFFE( _LC5_E20, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:32' 
-- Equation name is '_LC2_E20', type is buried 
_LC2_E20 = DFFE( _LC3_E20, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:34' 
-- Equation name is '_LC4_F35', type is buried 
_LC4_F35 = DFFE( _LC3_F4, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:36' 
-- Equation name is '_LC6_F1', type is buried 
_LC6_F1  = DFFE( _LC2_F1, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:38' 
-- Equation name is '_LC8_F1', type is buried 
_LC8_F1  = DFFE( _LC6_F12, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:40' 
-- Equation name is '_LC1_F1', type is buried 
_LC1_F1  = DFFE( _LC2_F12, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:42' 
-- Equation name is '_LC8_F3', type is buried 
_LC8_F3  = DFFE( _LC5_F5, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:44' 
-- Equation name is '_LC1_F5', type is buried 
_LC1_F5  = DFFE( _LC7_F5, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:46' 
-- Equation name is '_LC6_F5', type is buried 
_LC6_F5  = DFFE( _LC7_F7, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:48' 
-- Equation name is '_LC1_F8', type is buried 
_LC1_F8  = DFFE( _LC8_F7, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:50' 
-- Equation name is '_LC2_F8', type is buried 
_LC2_F8  = DFFE( _LC6_F20, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:52' 
-- Equation name is '_LC2_F9', type is buried 
_LC2_F9  = DFFE( _LC3_F20, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:54' 
-- Equation name is '_LC4_F27', type is buried 
_LC4_F27 = DFFE( _LC5_F30, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:56' 
-- Equation name is '_LC2_F31', type is buried 
_LC2_F31 = DFFE( _LC1_F30, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:58' 
-- Equation name is '_LC1_F34', type is buried 
_LC1_F34 = DFFE( _LC2_F26, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:60' 
-- Equation name is '_LC2_F34', type is buried 
_LC2_F34 = DFFE( _LC1_F26, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:62' 
-- Equation name is '_LC2_F35', type is buried 
_LC2_F35 = DFFE( _LC5_F1, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:64' 
-- Equation name is '_LC8_F35', type is buried 
_LC8_F35 = DFFE( _LC6_F26, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:66' 
-- Equation name is '_LC7_F35', type is buried 
_LC7_F35 = DFFE( _LC3_F25, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:68' 
-- Equation name is '_LC5_F35', type is buried 
_LC5_F35 = DFFE( _LC8_F25, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:70' 
-- Equation name is '_LC3_F7', type is buried 
_LC3_F7  = DFFE( _LC7_F25, !_LC3_F35,  VCC,  VCC,  VCC);

-- Node name is '|REG24B:U2|:72' 
-- Equation name is '_LC1_F7', type is buried 
_LC1_F7  = DFFE( _LC1_F25, !_LC3_F35,  VCC,  VCC,  VCC);



Project Information              d:\02010231\24wei10jinzhipinlvji\freqtest.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,538K