📄 freqtest.rpt
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Total single-pin Output Enables required: 0
Synthesized logic cells: 39/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 16/0
F: 8 0 1 8 8 0 8 2 1 0 0 8 0 0 0 0 0 0 0 0 8 0 0 0 0 8 8 2 0 0 8 1 0 0 2 8 0 89/0
Total: 8 0 1 8 8 0 8 2 1 0 0 8 0 0 0 0 0 0 0 0 16 0 0 0 0 8 8 2 0 0 8 1 0 8 2 8 0 105/0
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\freqtest.rpt
freqtest
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 1 CLK1HZ
54 - - - -- INPUT G ^ 0 0 0 0 FSIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\freqtest.rpt
freqtest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 DOUT0
31 - - F -- OUTPUT 0 1 0 0 DOUT1
32 - - F -- OUTPUT 0 1 0 0 DOUT2
33 - - F -- OUTPUT 0 1 0 0 DOUT3
36 - - - 36 OUTPUT 0 1 0 0 DOUT4
37 - - - 35 OUTPUT 0 1 0 0 DOUT5
38 - - - 34 OUTPUT 0 1 0 0 DOUT6
39 - - - 33 OUTPUT 0 1 0 0 DOUT7
41 - - - 31 OUTPUT 0 1 0 0 DOUT8
42 - - - 28 OUTPUT 0 1 0 0 DOUT9
65 - - - 09 OUTPUT 0 1 0 0 DOUT10
67 - - - 08 OUTPUT 0 1 0 0 DOUT11
68 - - - 07 OUTPUT 0 1 0 0 DOUT12
69 - - - 06 OUTPUT 0 1 0 0 DOUT13
70 - - - 05 OUTPUT 0 1 0 0 DOUT14
72 - - - 03 OUTPUT 0 1 0 0 DOUT15
73 - - - 01 OUTPUT 0 1 0 0 DOUT16
78 - - F -- OUTPUT 0 1 0 0 DOUT17
79 - - F -- OUTPUT 0 1 0 0 DOUT18
80 - - F -- OUTPUT 0 1 0 0 DOUT19
81 - - F -- OUTPUT 0 1 0 0 DOUT20
82 - - F -- OUTPUT 0 1 0 0 DOUT21
83 - - E -- OUTPUT 0 1 0 0 DOUT22
86 - - E -- OUTPUT 0 1 0 0 DOUT23
29 - - E -- OUTPUT 0 1 0 0 SHOW
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\freqtest.rpt
freqtest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 25 AND2 0 2 0 1 |COUNTER24B:U3|LPM_ADD_SUB:298|addcore:adder|:55
- 6 - F 25 OR2 0 4 0 1 |COUNTER24B:U3|LPM_ADD_SUB:298|addcore:adder|:69
- 6 - F 35 OR2 ! 0 2 0 3 |COUNTER24B:U3|LPM_ADD_SUB:398|addcore:adder|:55
- 1 - F 27 OR2 ! 0 2 0 3 |COUNTER24B:U3|LPM_ADD_SUB:498|addcore:adder|:55
- 6 - F 07 OR2 ! 0 2 0 3 |COUNTER24B:U3|LPM_ADD_SUB:598|addcore:adder|:55
- 3 - F 01 OR2 ! 0 2 0 3 |COUNTER24B:U3|LPM_ADD_SUB:698|addcore:adder|:55
- 4 - E 33 AND2 0 2 0 4 |COUNTER24B:U3|LPM_ADD_SUB:785|addcore:adder|:55
- 3 - F 25 DFFE + 0 4 0 3 |COUNTER24B:U3|Q03 (|COUNTER24B:U3|:29)
- 8 - F 25 DFFE + 0 4 0 4 |COUNTER24B:U3|Q02 (|COUNTER24B:U3|:30)
- 7 - F 25 DFFE + 0 4 0 5 |COUNTER24B:U3|Q01 (|COUNTER24B:U3|:31)
- 1 - F 25 DFFE + 0 3 0 7 |COUNTER24B:U3|Q00 (|COUNTER24B:U3|:32)
- 2 - F 26 DFFE + 0 4 0 2 |COUNTER24B:U3|Q13 (|COUNTER24B:U3|:33)
- 1 - F 26 DFFE + 0 4 0 5 |COUNTER24B:U3|Q12 (|COUNTER24B:U3|:34)
- 5 - F 01 DFFE + 0 4 0 4 |COUNTER24B:U3|Q11 (|COUNTER24B:U3|:35)
- 6 - F 26 DFFE + 0 4 0 7 |COUNTER24B:U3|Q10 (|COUNTER24B:U3|:36)
- 6 - F 20 DFFE + 0 4 0 2 |COUNTER24B:U3|Q23 (|COUNTER24B:U3|:37)
- 3 - F 20 DFFE + 0 4 0 5 |COUNTER24B:U3|Q22 (|COUNTER24B:U3|:38)
- 5 - F 30 DFFE + 0 4 0 4 |COUNTER24B:U3|Q21 (|COUNTER24B:U3|:39)
- 1 - F 30 DFFE + 0 4 0 7 |COUNTER24B:U3|Q20 (|COUNTER24B:U3|:40)
- 5 - F 05 DFFE + 0 4 0 3 |COUNTER24B:U3|Q33 (|COUNTER24B:U3|:41)
- 7 - F 05 DFFE + 0 4 0 4 |COUNTER24B:U3|Q32 (|COUNTER24B:U3|:42)
- 7 - F 07 DFFE + 0 4 0 3 |COUNTER24B:U3|Q31 (|COUNTER24B:U3|:43)
- 8 - F 07 DFFE + 0 4 0 8 |COUNTER24B:U3|Q30 (|COUNTER24B:U3|:44)
- 3 - F 04 DFFE + 0 4 0 2 |COUNTER24B:U3|Q43 (|COUNTER24B:U3|:45)
- 2 - F 01 DFFE + 0 4 0 4 |COUNTER24B:U3|Q42 (|COUNTER24B:U3|:46)
- 6 - F 12 DFFE + 0 4 0 3 |COUNTER24B:U3|Q41 (|COUNTER24B:U3|:47)
- 2 - F 12 DFFE + 0 4 0 10 |COUNTER24B:U3|Q40 (|COUNTER24B:U3|:48)
- 3 - E 33 DFFE + 0 4 0 3 |COUNTER24B:U3|Q53 (|COUNTER24B:U3|:49)
- 1 - E 33 DFFE + 0 4 0 5 |COUNTER24B:U3|Q52 (|COUNTER24B:U3|:50)
- 5 - E 20 DFFE + 0 4 0 4 |COUNTER24B:U3|Q51 (|COUNTER24B:U3|:51)
- 3 - E 20 DFFE + 0 3 0 6 |COUNTER24B:U3|Q50 (|COUNTER24B:U3|:52)
- 6 - E 20 DFFE + 0 4 1 0 |COUNTER24B:U3|C5 (|COUNTER24B:U3|:53)
- 4 - F 25 AND2 s 0 4 0 4 |COUNTER24B:U3|~239~1
- 3 - F 26 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~2
- 7 - F 26 AND2 s 0 3 0 2 |COUNTER24B:U3|~239~3
- 1 - F 35 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~4
- 6 - F 30 AND2 s 0 4 0 4 |COUNTER24B:U3|~239~5
- 7 - F 30 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~6
- 2 - F 20 AND2 s 0 3 0 2 |COUNTER24B:U3|~239~7
- 4 - F 20 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~8
- 7 - F 20 OR2 s ! 0 4 0 4 |COUNTER24B:U3|~239~9
- 4 - F 07 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~10
- 3 - F 05 AND2 s 0 3 0 2 |COUNTER24B:U3|~239~11
- 4 - F 05 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~12
- 3 - F 12 AND2 s 0 4 0 4 |COUNTER24B:U3|~239~13
- 7 - F 12 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~14
- 8 - F 12 AND2 s 0 3 0 2 |COUNTER24B:U3|~239~15
- 4 - F 01 AND2 s 0 2 0 1 |COUNTER24B:U3|~239~16
- 1 - F 04 AND2 s 0 3 0 4 |COUNTER24B:U3|~239~17
- 7 - E 33 AND2 s 0 3 0 1 |COUNTER24B:U3|~239~18
- 2 - F 25 OR2 0 4 0 5 |COUNTER24B:U3|:239
- 2 - F 30 OR2 0 4 0 2 |COUNTER24B:U3|:339
- 1 - F 20 OR2 0 4 0 2 |COUNTER24B:U3|:439
- 2 - F 05 AND2 ! 0 2 0 2 |COUNTER24B:U3|:565
- 6 - F 04 OR2 0 3 0 3 |COUNTER24B:U3|:639
- 5 - F 04 AND2 ! 0 2 0 3 |COUNTER24B:U3|:665
- 2 - E 33 OR2 0 4 0 4 |COUNTER24B:U3|:734
- 8 - E 20 AND2 0 3 0 1 |COUNTER24B:U3|:736
- 2 - F 04 AND2 s 0 2 0 6 |COUNTER24B:U3|~1121~1
- 1 - F 12 OR2 s 0 4 0 6 |COUNTER24B:U3|~1395~1
- 5 - F 20 AND2 s 0 2 0 6 |COUNTER24B:U3|~1734~1
- 3 - F 30 AND2 s 0 2 0 6 |COUNTER24B:U3|~2138~1
- 8 - F 04 AND2 s ! 0 3 0 1 |COUNTER24B:U3|~2305~1
- 6 - E 33 OR2 s 0 4 0 1 |COUNTER24B:U3|~2305~2
- 5 - E 33 OR2 s 0 4 0 1 |COUNTER24B:U3|~2311~1
- 7 - E 20 OR2 s 0 4 0 1 |COUNTER24B:U3|~2317~1
- 4 - F 04 OR2 s 0 4 0 5 |COUNTER24B:U3|~2323~1
- 7 - F 04 OR2 s 0 4 0 1 |COUNTER24B:U3|~2329~1
- 5 - F 12 OR2 s 0 3 0 1 |COUNTER24B:U3|~2341~1
- 4 - F 12 OR2 s 0 2 0 6 |COUNTER24B:U3|~2347~1
- 8 - F 05 OR2 s 0 4 0 1 |COUNTER24B:U3|~2353~1
- 2 - F 07 OR2 s 0 3 0 1 |COUNTER24B:U3|~2365~1
- 5 - F 07 OR2 s 0 2 0 5 |COUNTER24B:U3|~2371~1
- 8 - F 20 OR2 s 0 4 0 1 |COUNTER24B:U3|~2377~1
- 4 - F 30 OR2 s 0 3 0 1 |COUNTER24B:U3|~2389~1
- 8 - F 30 OR2 s 0 2 0 5 |COUNTER24B:U3|~2395~1
- 8 - F 26 OR2 s 0 4 0 1 |COUNTER24B:U3|~2401~1
- 5 - F 26 OR2 s 0 3 0 1 |COUNTER24B:U3|~2413~1
- 4 - F 26 OR2 s 0 2 0 5 |COUNTER24B:U3|~2419~1
- 3 - F 35 DFFE + 0 0 0 30 |FTCTRL:U1|Div2CLK (|FTCTRL:U1|:5)
- 7 - F 01 OR2 ! 1 1 0 25 |FTCTRL:U1|:36
- 4 - E 20 DFFE 0 2 1 0 |REG24B:U2|:26
- 8 - E 33 DFFE 0 2 1 0 |REG24B:U2|:28
- 1 - E 20 DFFE 0 2 1 0 |REG24B:U2|:30
- 2 - E 20 DFFE 0 2 1 0 |REG24B:U2|:32
- 4 - F 35 DFFE 0 2 1 0 |REG24B:U2|:34
- 6 - F 01 DFFE 0 2 1 0 |REG24B:U2|:36
- 8 - F 01 DFFE 0 2 1 0 |REG24B:U2|:38
- 1 - F 01 DFFE 0 2 1 0 |REG24B:U2|:40
- 8 - F 03 DFFE 0 2 1 0 |REG24B:U2|:42
- 1 - F 05 DFFE 0 2 1 0 |REG24B:U2|:44
- 6 - F 05 DFFE 0 2 1 0 |REG24B:U2|:46
- 1 - F 08 DFFE 0 2 1 0 |REG24B:U2|:48
- 2 - F 08 DFFE 0 2 1 0 |REG24B:U2|:50
- 2 - F 09 DFFE 0 2 1 0 |REG24B:U2|:52
- 4 - F 27 DFFE 0 2 1 0 |REG24B:U2|:54
- 2 - F 31 DFFE 0 2 1 0 |REG24B:U2|:56
- 1 - F 34 DFFE 0 2 1 0 |REG24B:U2|:58
- 2 - F 34 DFFE 0 2 1 0 |REG24B:U2|:60
- 2 - F 35 DFFE 0 2 1 0 |REG24B:U2|:62
- 8 - F 35 DFFE 0 2 1 0 |REG24B:U2|:64
- 7 - F 35 DFFE 0 2 1 0 |REG24B:U2|:66
- 5 - F 35 DFFE 0 2 1 0 |REG24B:U2|:68
- 3 - F 07 DFFE 0 2 1 0 |REG24B:U2|:70
- 1 - F 07 DFFE 0 2 1 0 |REG24B:U2|:72
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\freqtest.rpt
freqtest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 11/144( 7%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 46/144( 31%) 3/ 72( 4%) 6/ 72( 8%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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