counter24b.rpt

可编程逻辑设计的程序！24位十进制频率计！可使ＥＤＡ实验年箱测量指定频率！

_LC1_B23~NOT = LCELL( _EQ049);
  _EQ049 = !Q31
         # !Q30;

-- Node name is '|LPM_ADD_SUB:698|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B22', type is buried 
!_LC3_B22 = _LC3_B22~NOT;
_LC3_B22~NOT = LCELL( _EQ050);
  _EQ050 = !Q41
         # !Q40;

-- Node name is ':239' 
-- Equation name is '_LC2_A10', type is buried 
_LC2_A10 = LCELL( _EQ051);
  _EQ051 = !Q03
         # !Q00 & !Q01 & !Q02;

-- Node name is ':339' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ052);
  _EQ052 = !Q13
         # !Q10 & !Q11 & !Q12;

-- Node name is ':439' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = LCELL( _EQ053);
  _EQ053 = !Q23
         # !Q20 & !Q21 & !Q22;

-- Node name is ':565' 
-- Equation name is '_LC5_B13', type is buried 
!_LC5_B13 = _LC5_B13~NOT;
_LC5_B13~NOT = LCELL( _EQ054);
  _EQ054 = !Q31 & !Q32;

-- Node name is ':665' 
-- Equation name is '_LC1_B22', type is buried 
!_LC1_B22 = _LC1_B22~NOT;
_LC1_B22~NOT = LCELL( _EQ055);
  _EQ055 = !Q41 & !Q42;

-- Node name is ':734' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ056);
  _EQ056 = !Q53
         # !Q50 & !Q51 & !Q52;

-- Node name is ':736' 
-- Equation name is '_LC7_B22', type is buried 
_LC7_B22 = LCELL( _EQ057);
  _EQ057 = !Q50 & !Q51 & !Q52;

-- Node name is '~1121~1' 
-- Equation name is '~1121~1', location is LC2_B19, type is buried.
-- synthesized logic cell 
_LC2_B19 = LCELL( _EQ058);
  _EQ058 =  Q30 & !Q43
         # !_LC1_B22 &  Q30 & !Q40;

-- Node name is '~1395~1' 
-- Equation name is '~1395~1', location is LC2_B13, type is buried.
-- synthesized logic cell 
_LC2_B13 = LCELL( _EQ059);
  _EQ059 =  Q20 & !Q33
         # !_LC5_B13 &  Q20 & !Q30;

-- Node name is '~1734~1' 
-- Equation name is '~1734~1', location is LC1_A18, type is buried.
-- synthesized logic cell 
_LC1_A18 = LCELL( _EQ060);
  _EQ060 =  _LC2_A24 &  Q10;

-- Node name is '~2138~1' 
-- Equation name is '~2138~1', location is LC2_A23, type is buried.
-- synthesized logic cell 
_LC2_A23 = LCELL( _EQ061);
  _EQ061 =  _LC3_A23 &  Q00;

-- Node name is '~2299~1' 
-- Equation name is '~2299~1', location is LC1_B19, type is buried.
-- synthesized logic cell 
!_LC1_B19 = _LC1_B19~NOT;
_LC1_B19~NOT = LCELL( _EQ062);
  _EQ062 = !_LC1_B22 & !_LC4_B13 &  Q40 &  Q43;

-- Node name is '~2305~1' 
-- Equation name is '~2305~1', location is LC4_B22, type is buried.
-- synthesized logic cell 
_LC4_B22 = LCELL( _EQ063);
  _EQ063 = !Q51
         # !Q50
         # !Q52;

-- Node name is '~2305~2' 
-- Equation name is '~2305~2', location is LC5_B22, type is buried.
-- synthesized logic cell 
_LC5_B22 = LCELL( _EQ064);
  _EQ064 =  _LC1_B15 &  _LC4_B22 &  Q40
         #  _LC3_B19;

-- Node name is '~2317~1' 
-- Equation name is '~2317~1', location is LC2_B15, type is buried.
-- synthesized logic cell 
_LC2_B15 = LCELL( _EQ065);
  _EQ065 =  _LC1_B15 &  Q40 & !Q50
         #  _LC3_B19;

-- Node name is '~2323~1' 
-- Equation name is '~2323~1', location is LC3_B19, type is buried.
-- synthesized logic cell 
_LC3_B19 = LCELL( _EQ066);
  _EQ066 = !Q43
         #  _LC1_B22
         #  _LC4_B13
         # !Q40;

-- Node name is '~2329~1' 
-- Equation name is '~2329~1', location is LC6_B19, type is buried.
-- synthesized logic cell 
_LC6_B19 = LCELL( _EQ067);
  _EQ067 =  _LC2_B19 & !Q42
         #  _LC2_B19 & !_LC3_B22
         #  _LC4_B13;

-- Node name is '~2341~1' 
-- Equation name is '~2341~1', location is LC7_B13, type is buried.
-- synthesized logic cell 
_LC7_B13 = LCELL( _EQ068);
  _EQ068 =  _LC2_B19 & !Q40
         #  _LC4_B13;

-- Node name is '~2347~1' 
-- Equation name is '~2347~1', location is LC4_B13, type is buried.
-- synthesized logic cell 
_LC4_B13 = LCELL( _EQ069);
  _EQ069 = !_LC3_B13
         # !Q30;

-- Node name is '~2353~1' 
-- Equation name is '~2353~1', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ070);
  _EQ070 =  _LC2_B13 & !Q32
         # !_LC1_B23 &  _LC2_B13
         #  _LC5_B23;

-- Node name is '~2365~1' 
-- Equation name is '~2365~1', location is LC1_B16, type is buried.
-- synthesized logic cell 
_LC1_B16 = LCELL( _EQ071);
  _EQ071 =  _LC2_B13 & !Q30
         #  _LC5_B23;

-- Node name is '~2371~1' 
-- Equation name is '~2371~1', location is LC5_B23, type is buried.
-- synthesized logic cell 
_LC5_B23 = LCELL( _EQ072);
  _EQ072 = !_LC6_A24
         # !Q20;

-- Node name is '~2377~1' 
-- Equation name is '~2377~1', location is LC5_A24, type is buried.
-- synthesized logic cell 
_LC5_A24 = LCELL( _EQ073);
  _EQ073 =  _LC1_A18 & !Q22
         #  _LC1_A18 & !_LC1_A24
         #  _LC4_A23;

-- Node name is '~2389~1' 
-- Equation name is '~2389~1', location is LC7_A23, type is buried.
-- synthesized logic cell 
_LC7_A23 = LCELL( _EQ074);
  _EQ074 =  _LC1_A18 & !Q20
         #  _LC4_A23;

-- Node name is '~2395~1' 
-- Equation name is '~2395~1', location is LC4_A23, type is buried.
-- synthesized logic cell 
_LC4_A23 = LCELL( _EQ075);
  _EQ075 = !_LC6_A23
         # !Q10;

-- Node name is '~2401~1' 
-- Equation name is '~2401~1', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( _EQ076);
  _EQ076 =  _LC2_A23 & !Q12
         #  _LC2_A23 & !_LC3_A13
         #  _LC4_A13;

-- Node name is '~2413~1' 
-- Equation name is '~2413~1', location is LC3_A18, type is buried.
-- synthesized logic cell 
_LC3_A18 = LCELL( _EQ077);
  _EQ077 =  _LC2_A23 & !Q10
         #  _LC4_A13;

-- Node name is '~2419~1' 
-- Equation name is '~2419~1', location is LC4_A13, type is buried.
-- synthesized logic cell 
_LC4_A13 = LCELL( _EQ078);
  _EQ078 = !_LC8_A10
         # !Q00;



Project Information            d:\02010231\24wei10jinzhipinlvji\counter24b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,944K