📄 counter24b.rpt
字号:
63 - - B -- OUTPUT 0 1 0 0 DOUT21
16 - - B -- OUTPUT 0 1 0 0 DOUT22
96 - - - 22 OUTPUT 0 1 0 0 DOUT23
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\counter24b.rpt
counter24b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 10 AND2 s 1 3 0 4 ENABL~1
- 4 - A 18 AND2 s 0 2 0 1 ENABL~2
- 5 - A 13 AND2 s 0 3 0 2 ENABL~3
- 6 - A 13 AND2 s 0 2 0 1 ENABL~4
- 6 - A 23 AND2 s 0 4 0 4 ENABL~5
- 8 - A 23 AND2 s 0 2 0 1 ENABL~6
- 3 - A 24 AND2 s 0 3 0 2 ENABL~7
- 4 - A 24 AND2 s 0 2 0 1 ENABL~8
- 6 - A 24 OR2 s ! 0 4 0 4 ENABL~9
- 2 - B 16 AND2 s 0 2 0 1 ENABL~10
- 4 - B 23 AND2 s 0 3 0 2 ENABL~11
- 7 - B 23 AND2 s 0 2 0 1 ENABL~12
- 3 - B 13 AND2 s 0 4 0 4 ENABL~13
- 8 - B 13 AND2 s 0 2 0 1 ENABL~14
- 4 - B 19 AND2 s 0 3 0 2 ENABL~15
- 5 - B 19 AND2 s 0 2 0 1 ENABL~16
- 6 - B 15 AND2 s 0 3 0 4 ENABL~17
- 3 - B 15 OR2 s 0 4 0 1 ENABL~18
- 8 - B 15 AND2 s 0 4 0 1 ENABL~19
- 5 - A 10 AND2 0 2 0 1 |LPM_ADD_SUB:298|addcore:adder|:55
- 7 - A 10 OR2 0 4 0 1 |LPM_ADD_SUB:298|addcore:adder|:69
- 3 - A 13 OR2 ! 0 2 0 3 |LPM_ADD_SUB:398|addcore:adder|:55
- 1 - A 24 OR2 ! 0 2 0 3 |LPM_ADD_SUB:498|addcore:adder|:55
- 1 - B 23 OR2 ! 0 2 0 3 |LPM_ADD_SUB:598|addcore:adder|:55
- 3 - B 22 OR2 ! 0 2 0 3 |LPM_ADD_SUB:698|addcore:adder|:55
- 1 - A 10 DFFE + 1 2 1 2 Q03 (:29)
- 4 - A 10 DFFE + 1 2 1 3 Q02 (:30)
- 3 - A 10 DFFE + 1 2 1 4 Q01 (:31)
- 6 - A 10 DFFE + 1 1 1 6 Q00 (:32)
- 2 - A 13 DFFE + 0 3 1 1 Q13 (:33)
- 7 - A 13 DFFE + 0 3 1 4 Q12 (:34)
- 2 - A 18 DFFE + 0 3 1 3 Q11 (:35)
- 1 - A 13 DFFE + 0 3 1 6 Q10 (:36)
- 7 - A 24 DFFE + 0 3 1 1 Q23 (:37)
- 8 - A 24 DFFE + 0 3 1 4 Q22 (:38)
- 5 - A 23 DFFE + 0 3 1 3 Q21 (:39)
- 1 - A 23 DFFE + 0 3 1 6 Q20 (:40)
- 3 - B 23 DFFE + 0 3 1 2 Q33 (:41)
- 2 - B 23 DFFE + 0 3 1 3 Q32 (:42)
- 5 - B 16 DFFE + 0 3 1 2 Q31 (:43)
- 6 - B 23 DFFE + 0 3 1 7 Q30 (:44)
- 7 - B 19 DFFE + 0 3 1 3 Q43 (:45)
- 8 - B 19 DFFE + 0 3 1 3 Q42 (:46)
- 6 - B 13 DFFE + 0 3 1 2 Q41 (:47)
- 1 - B 13 DFFE + 0 3 1 10 Q40 (:48)
- 2 - B 22 DFFE + 0 3 1 2 Q53 (:49)
- 7 - B 15 DFFE + 0 3 1 4 Q52 (:50)
- 4 - B 15 DFFE + 0 3 1 5 Q51 (:51)
- 5 - B 15 DFFE + 0 2 1 7 Q50 (:52)
- 6 - B 22 DFFE + 0 3 1 0 C5 (:53)
- 2 - A 10 OR2 0 4 0 5 :239
- 3 - A 23 OR2 0 4 0 2 :339
- 2 - A 24 OR2 0 4 0 2 :439
- 5 - B 13 AND2 ! 0 2 0 2 :565
- 1 - B 22 AND2 ! 0 2 0 3 :665
- 1 - B 15 OR2 0 4 0 4 :734
- 7 - B 22 AND2 0 3 0 1 :736
- 2 - B 19 OR2 s 0 4 0 6 ~1121~1
- 2 - B 13 OR2 s 0 4 0 6 ~1395~1
- 1 - A 18 AND2 s 0 2 0 6 ~1734~1
- 2 - A 23 AND2 s 0 2 0 6 ~2138~1
- 1 - B 19 AND2 s ! 0 4 0 1 ~2299~1
- 4 - B 22 OR2 s 0 3 0 2 ~2305~1
- 5 - B 22 OR2 s 0 4 0 1 ~2305~2
- 2 - B 15 OR2 s 0 4 0 1 ~2317~1
- 3 - B 19 OR2 s 0 4 0 5 ~2323~1
- 6 - B 19 OR2 s 0 4 0 1 ~2329~1
- 7 - B 13 OR2 s 0 3 0 1 ~2341~1
- 4 - B 13 OR2 s 0 2 0 6 ~2347~1
- 8 - B 23 OR2 s 0 4 0 1 ~2353~1
- 1 - B 16 OR2 s 0 3 0 1 ~2365~1
- 5 - B 23 OR2 s 0 2 0 5 ~2371~1
- 5 - A 24 OR2 s 0 4 0 1 ~2377~1
- 7 - A 23 OR2 s 0 3 0 1 ~2389~1
- 4 - A 23 OR2 s 0 2 0 5 ~2395~1
- 8 - A 13 OR2 s 0 4 0 1 ~2401~1
- 3 - A 18 OR2 s 0 3 0 1 ~2413~1
- 4 - A 13 OR2 s 0 2 0 5 ~2419~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\counter24b.rpt
counter24b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 3/ 48( 6%) 6/ 48( 12%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
B: 21/ 96( 21%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\counter24b.rpt
counter24b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 FIN
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\counter24b.rpt
counter24b
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 25 CLR
Device-Specific Information: d:\02010231\24wei10jinzhipinlvji\counter24b.rpt
counter24b
** EQUATIONS **
CLR : INPUT;
ENABL : INPUT;
FIN : INPUT;
-- Node name is 'COUT'
-- Equation name is 'COUT', type is output
COUT = C5;
-- Node name is ':53' = 'C5'
-- Equation name is 'C5', location is LC6_B22, type is buried.
C5 = DFFE( _EQ001, GLOBAL( FIN), GLOBAL(!CLR), VCC, VCC);
_EQ001 = !_LC3_B19 & !_LC7_B22 & Q53
# C5 & _LC7_B22
# C5 & !Q53
# C5 & _LC3_B19;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = Q00;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = Q01;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = Q02;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = Q03;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = Q10;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = Q11;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = Q12;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = Q13;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = Q20;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = Q21;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = Q22;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = Q23;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = Q30;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = Q31;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = Q32;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = Q33;
-- Node name is 'DOUT16'
-- Equation name is 'DOUT16', type is output
DOUT16 = Q40;
-- Node name is 'DOUT17'
-- Equation name is 'DOUT17', type is output
DOUT17 = Q41;
-- Node name is 'DOUT18'
-- Equation name is 'DOUT18', type is output
DOUT18 = Q42;
-- Node name is 'DOUT19'
-- Equation name is 'DOUT19', type is output
DOUT19 = Q43;
-- Node name is 'DOUT20'
-- Equation name is 'DOUT20', type is output
DOUT20 = Q50;
-- Node name is 'DOUT21'
-- Equation name is 'DOUT21', type is output
DOUT21 = Q51;
-- Node name is 'DOUT22'
-- Equation name is 'DOUT22', type is output
DOUT22 = Q52;
-- Node name is 'DOUT23'
-- Equation name is 'DOUT23', type is output
DOUT23 = Q53;
-- Node name is 'ENABL~1'
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