reg2812.h

f2812头文件

/*F2812	
*************************************************************************************
* 	F2812.h																			*	
************************************************************************************/
extern cregister volatile unsigned int IER;
extern cregister volatile unsigned int IFR;

/*-----Peripheral Frame 0 Registers--------------------------------------------------------------------
	0x800~0xcff
	Registers in Frame 0 support 16-bit and 32-bit accesses
*/
//-----Device Emulation Registers----------------------------------------------------------------------
//#define DEVICECNF 0x0000 0880 0x0000 0881 2 Device Configuration Register
//#define DEVICEID 0x0000 0882 0x0000 0883 2 Device ID Register
#define PROTSTART 	*((volatile unsigned int *)0x0884) 	// Block Protection Start Address Register
#define PROTRANGE 	*((volatile unsigned int *)0x0885) 	// Block Protection Range Address Register

//-----PIE Configuration Registers---------------------------------------------------------------------
#define PIECTRL     *((volatile unsigned int *)0x0CE0)	// PIE, Control Register	
#define PIEACK      *((volatile unsigned int *)0x0CE1)	// PIE, Acknowledge Register 
#define PIEIER1     *((volatile unsigned int *)0x0CE2)	// PIE, INT1 Group Enable Register 
#define PIEIFR1 	*((volatile unsigned int *)0x0CE3)  // PIE, INT1 Group Flag Register
#define PIEIER2 	*((volatile unsigned int *)0x0CE4)  // PIE, INT2 Group Enable Register
#define PIEIFR2 	*((volatile unsigned int *)0x0CE5)  // PIE, INT2 Group Flag Register
#define PIEIER3 	*((volatile unsigned int *)0x0CE6)  // PIE, INT3 Group Enable Register
#define PIEIFR3 	*((volatile unsigned int *)0x0CE7)  // PIE, INT3 Group Flag Register
#define PIEIER4 	*((volatile unsigned int *)0x0CE8)  // PIE, INT4 Group Enable Register
#define PIEIFR4 	*((volatile unsigned int *)0x0CE9)  // PIE, INT4 Group Flag Register
#define PIEIER5 	*((volatile unsigned int *)0x0CEA)  // PIE, INT5 Group Enable Register
#define PIEIFR5 	*((volatile unsigned int *)0x0CEB)  // PIE, INT5 Group Flag Register
#define PIEIER6 	*((volatile unsigned int *)0x0CEC)  // PIE, INT6 Group Enable Register
#define PIEIFR6 	*((volatile unsigned int *)0x0CED)  // PIE, INT6 Group Flag Register
#define PIEIER7 	*((volatile unsigned int *)0x0CEE)  // PIE, INT7 Group Enable Register
#define PIEIFR7 	*((volatile unsigned int *)0x0CEF)  // PIE, INT7 Group Flag Register
#define PIEIER8 	*((volatile unsigned int *)0x0CF0)  // PIE, INT8 Group Enable Register
#define PIEIFR8 	*((volatile unsigned int *)0x0CF1)  // PIE, INT8 Group Flag Register
#define PIEIER9 	*((volatile unsigned int *)0x0CF2)  // PIE, INT9 Group Enable Register
#define PIEIFR9 	*((volatile unsigned int *)0x0CF3)  // PIE, INT9 Group Flag Register
#define PIEIER10 	*((volatile unsigned int *)0x0CF4)  // PIE, INT10 Group Enable Register
#define PIEIFR10 	*((volatile unsigned int *)0x0CF5)  // PIE, INT10 Group Flag Register
#define PIEIER11 	*((volatile unsigned int *)0x0CF6)  // PIE, INT11 Group Enable Register
#define PIEIFR11 	*((volatile unsigned int *)0x0CF7)  // PIE, INT11 Group Flag Register
#define PIEIER12 	*((volatile unsigned int *)0x0CF8)  // PIE, INT12 Group Enable Register
#define PIEIFR12 	*((volatile unsigned int *)0x0CF9)  // PIE, INT12 Group Flag Register

//-----CPU-Timers 0, 1, 2 Configuration and Control Registers------------------------------------------
#define TIMER0TIM 	*((volatile unsigned int *)0x0C00)	// CPU-Timer 0, Counter Register
#define TIMER0TIMH 	*((volatile unsigned int *)0x0C01)	// CPU-Timer 0, Counter Register High
#define TIMER0PRD 	*((volatile unsigned int *)0x0C02)	// CPU-Timer 0, Period Register
#define TIMER0PRDH 	*((volatile unsigned int *)0x0C03)	// CPU-Timer 0, Period Register High
#define TIMER0TCR 	*((volatile unsigned int *)0x0C04)	// CPU-Timer 0, Control Register
#define TIMER0TPR 	*((volatile unsigned int *)0x0C06)	// CPU-Timer 0, Prescale Register
#define TIMER0TPRH 	*((volatile unsigned int *)0x0C07)	// CPU-Timer 0, Prescale Register High
#define TIMER1TIM 	*((volatile unsigned int *)0x0C08)	// CPU-Timer 1, Counter Register
#define TIMER1TIMH 	*((volatile unsigned int *)0x0C09)	// CPU-Timer 1, Counter Register High
#define TIMER1PRD 	*((volatile unsigned int *)0x0C0A)	// CPU-Timer 1, Period Register
#define TIMER1PRDH 	*((volatile unsigned int *)0x0C0B)	// CPU-Timer 1, Period Register High
#define TIMER1TCR 	*((volatile unsigned int *)0x0C0C)	// CPU-Timer 1, Control Register
#define TIMER1TPR 	*((volatile unsigned int *)0x0C0E)	// CPU-Timer 1, Prescale Register
#define TIMER1TPRH 	*((volatile unsigned int *)0x0C0F)	// CPU-Timer 1, Prescale Register High
#define TIMER2TIM 	*((volatile unsigned int *)0x0C10)	// CPU-Timer 2, Counter Register
#define TIMER2TIMH 	*((volatile unsigned int *)0x0C11)	// CPU-Timer 2, Counter Register High
#define TIMER2PRD 	*((volatile unsigned int *)0x0C12)	// CPU-Timer 2, Period Register
#define TIMER2PRDH 	*((volatile unsigned int *)0x0C13)	// CPU-Timer 2, Period Register High
#define TIMER2TCR 	*((volatile unsigned int *)0x0C14)	// CPU-Timer 2, Control Register
#define TIMER2TPR 	*((volatile unsigned int *)0x0C16)	// CPU-Timer 2, Prescale Register
#define TIMER2TPRH 	*((volatile unsigned int *)0x0C17)	// CPU-Timer 2, Prescale Register High

/*-----Peripheral Frame 1 Registers--------------------------------------------------------------------
	0x6000~0x6fff
	The eCAN control registers only support 32-bit read/write operations. All 32-bit 
  accesses are aligned to even address boundaries
*/  
//-----eCAN Registers----------------------------------------------------------------------------------  
#define CANME 		*((volatile unsigned int *)0x6000)	// Mailbox enable
#define CANMD 		*((volatile unsigned int *)0x6002)	// Mailbox direction
#define CANTRS 		*((volatile unsigned int *)0x6004)	// Transmit request set
#define CANTRR 		*((volatile unsigned int *)0x6006)	// Transmit request reset
#define CANTA 		*((volatile unsigned int *)0x6008)	// Transmission acknowledge
#define CANAA 		*((volatile unsigned int *)0x600A)	// Abort acknowledge
#define CANRMP 		*((volatile unsigned int *)0x600C)	// Receive message pending
#define CANRML 		*((volatile unsigned int *)0x600E)	// Receive message lost
#define CANRFP 		*((volatile unsigned int *)0x6010)	// Remote frame pending
#define CANMC 		*((volatile unsigned int *)0x6014)	// Master control
#define CANBTC 		*((volatile unsigned int *)0x6016)	// Bit-timing configuration
#define CANES 		*((volatile unsigned int *)0x6018)	// Error and status
#define CANTEC 		*((volatile unsigned int *)0x601A)	// Transmit error counter
#define CANREC 		*((volatile unsigned int *)0x601C)	// Receive error counter
#define CANGIF0 	*((volatile unsigned int *)0x601E)	// Global interrupt flag 0
#define CANGIM 		*((volatile unsigned int *)0x6020)	// Global interrupt mask
#define CANGIF1 	*((volatile unsigned int *)0x6022)	// Global interrupt flag 1
#define CANMIM 		*((volatile unsigned int *)0x6024)	// Mailbox interrupt mask
#define CANMIL 		*((volatile unsigned int *)0x6026)	// Mailbox interrupt level
#define CANOPC 		*((volatile unsigned int *)0x6028)	// Overwrite protection control
#define CANTIOC 	*((volatile unsigned int *)0x602A)	// TX I/O control
#define CANRIOC 	*((volatile unsigned int *)0x602C)	// RX I/O control
#define CANLNT 		*((volatile unsigned int *)0x602E)	// Local network time (Reserved in SCC mode)
#define CANTOC 		*((volatile unsigned int *)0x6030)	// Time-out control (Reserved in SCC mode)
#define CANTOS 		*((volatile unsigned int *)0x6032)	// Time-out status (Reserved in SCC mode)

/*-----Peripheral Frame 2 Registers--------------------------------------------------------------------
		0x7000~0x7fff	Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored
eallow	edis*/	
//-----PLL, Clocking, Watchdog, and Low-Power Mode Registers-------------------------------------------
#define	HISPCP		*((volatile unsigned int *)0x701A)	// High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
#define LOSPCP 		*((volatile unsigned int *)0x701B)	// Low-Speed Peripheral Clock Prescaler Register for HSPCLK clock
#define PCLKCR 		*((volatile unsigned int *)0x701C) 	// Peripheral Clock Control Register
#define LPMCR0 		*((volatile unsigned int *)0x701E) 	// Low Power Mode Control Register 0
#define LPMCR1 		*((volatile unsigned int *)0x701F) 	// Low Power Mode Control Register 1
#define PLLCR 		*((volatile unsigned int *)0x7021) 	// PLL Control Register
#define SCSR 		*((volatile unsigned int *)0x7022) 	// System Control & Status Register
#define WDCNTR 		*((volatile unsigned int *)0x7023) 	// Watchdog Counter Register
#define WDKEY 		*((volatile unsigned int *)0x7025) 	// Watchdog Reset Key Register
#define WDCR 		*((volatile unsigned int *)0x7029) 	// Watchdog Control Register

//-----SPI Registers-----------------------------------------------------------------------------------
#define SPICCR 		*((volatile unsigned int *)0x7040)	// SPI Configuration Control Register
#define SPICTL 		*((volatile unsigned int *)0x7041)	// SPI Operation Control Register
#define SPIST 		*((volatile unsigned int *)0x7042)	// SPI Status Register
#define SPIBRR 		*((volatile unsigned int *)0x7044)	// SPI Baud Rate Register
#define SPIEMU 		*((volatile unsigned int *)0x7046)	// SPI Emulation Buffer Register
#define SPIRXBUF 	*((volatile unsigned int *)0x7047)	// SPI Serial Input Buffer Register
#define SPITXBUF 	*((volatile unsigned int *)0x7048)	// SPI Serial Output Buffer Register
#define SPIDAT 		*((volatile unsigned int *)0x7049)	// SPI Serial Data Register
#define SPIFFTX 	*((volatile unsigned int *)0x704A)	// SPI FIFO Transmit Register
#define SPIFFRX 	*((volatile unsigned int *)0x704B)	// SPI FIFO Receive Register
#define SPIFFCT 	*((volatile unsigned int *)0x704C)	// SPI FIFO Control Register
#define SPIPRI 		*((volatile unsigned int *)0x704F)	// SPI Priority Control Register
//-----SCI Registers-----------------------------------------------------------------------------------
//SCI-A Registers
#define SCICCR_A 	*((volatile unsigned int *)0x7050) 	// SCI-A Communications Control Register
#define SCICTL1_A 	*((volatile unsigned int *)0x7051) 	// SCI-A Control Register 1
#define SCIHBAUD_A 	*((volatile unsigned int *)0x7052) 	// SCI-A Baud Register, High Bits
#define SCILBAUD_A 	*((volatile unsigned int *)0x7053) 	// SCI-A Baud Register, Low Bits
#define SCICTL2_A 	*((volatile unsigned int *)0x7054) 	// SCI-A Control Register 2
#define SCIRXST_A 	*((volatile unsigned int *)0x7055) 	// SCI-A Receive Status Register
#define SCIRXEMU_A 	*((volatile unsigned int *)0x7056) 	// SCI-A Receive Emulation Data Buffer Register
#define SCIRXBUF_A 	*((volatile unsigned int *)0x7057) 	// SCI-A Receive Data Buffer Register
#define SCITXBUF_A 	*((volatile unsigned int *)0x7059) 	// SCI-A Transmit Data Buffer Register
#define SCIFFTX_A 	*((volatile unsigned int *)0x705A) 	// SCI-A FIFO Transmit Register
#define SCIFFRX_A 	*((volatile unsigned int *)0x705B) 	// SCI-A FIFO Receive Register