f281x.h

f2812内部ad转换程序

  /*   reserved 0x00 70D6 1  */
  /*   reserved 0x00 70D7 1  */
#define  GPGMUX  *((volatile unsigned int *)0x0070D8)  /*  1 GPIO G Mux Control Register */
#define  GPGDIR  *((volatile unsigned int *)0x0070D9)  /*  1 GPIO G Direction Control Register */
  /*   reserved 0x00 70DA 1
       reserved 0x00 70DB 1
       reserved 0x00 70DC ~ 0x00 70DF 4  */

     /*===================  GPIO Data Registers  ====================================*/
#define  GPADAT    *((volatile unsigned int *)0x0070E0)  /*   1 GPIO A Data Register  */
#define  GPASET    *((volatile unsigned int *)0x0070E1)  /*   1 GPIO A Set Register  */
#define  GPACLEAR  *((volatile unsigned int *)0x0070E2)  /*   1 GPIO A Clear Register  */
#define  GPATOGGLE *((volatile unsigned int *)0x0070E3)  /*   1 GPIO A Toggle Register  */
#define  GPBDAT    *((volatile unsigned int *)0x0070E4)  /*   1 GPIO B Data Register  */
#define  GPBSET    *((volatile unsigned int *)0x0070E5)  /*   1 GPIO B Set Register  */
#define  GPBCLEAR  *((volatile unsigned int *)0x0070E6)  /*   1 GPIO B Clear Register  */
#define  GPBTOGGLE *((volatile unsigned int *)0x0070E7)  /*   1 GPIO B Toggle Register  */
   /*  reserved 0x00 70E8 1 */
   /*  reserved 0x00 70E9 1 */
   /*  reserved 0x00 70EA 1 */
   /*  reserved 0x00 70EB 1 */
#define  GPDDAT    *((volatile unsigned int *)0x0070EC)  /*   1 GPIO D Data Register  */
#define  GPDSET    *((volatile unsigned int *)0x0070ED)  /*   1 GPIO D Set Register  */
#define  GPDCLEAR  *((volatile unsigned int *)0x0070EE)  /*   1 GPIO D Clear Register  */
#define  GPDTOGGLE *((volatile unsigned int *)0x0070EF)  /*   1 GPIO D Toggle Register  */
#define  GPEDAT    *((volatile unsigned int *)0x0070F0)  /*   1 GPIO E Data Register  */
#define  GPESET    *((volatile unsigned int *)0x0070F1)  /*   1 GPIO E Set Register  */
#define  GPECLEAR  *((volatile unsigned int *)0x0070F2)  /*   1 GPIO E Clear Register  */
#define  GPETOGGLE *((volatile unsigned int *)0x0070F3)  /*   1 GPIO E Toggle Register  */
#define  GPFDAT    *((volatile unsigned int *)0x0070F4)  /*   1 GPIO F Data Register  */
#define  GPFSET    *((volatile unsigned int *)0x0070F5)  /*   1 GPIO F Set Register  */
#define  GPFCLEAR  *((volatile unsigned int *)0x0070F6)  /*   1 GPIO F Clear Register  */
#define  GPFTOGGLE *((volatile unsigned int *)0x0070F7)  /*   1 GPIO F Toggle Register  */
#define  GPGDAT    *((volatile unsigned int *)0x0070F8)  /*   1 GPIO G Data Register  */
#define  GPGSET    *((volatile unsigned int *)0x0070F9)  /*   1 GPIO G Set Register  */
#define  GPGCLEAR  *((volatile unsigned int *)0x0070FA)  /*   1 GPIO G Clear Register  */
#define  GPGTOGGLE *((volatile unsigned int *)0x0070FB)  /*   1 GPIO G Toggle Register  */
   /*  reserved 0x00 70FC  ~  0x00 70FF  */



  /*==================    McBSP Register Summary   ============================*/
  /*        DATA REGISTERS, RECEIVE, TRANSMIT                                  */
/*      NAME         ADDRESS(0x0078xxh)      TYPE(R/W)  RESET VALUE   DESCRIPTION                       */
/*                                                       0x0000    McBSP Receive Buffer Register
                                                         0x0000    McBSP Receive Shift Register
                                                         0x0000    McBSP Transmit Shift Register
*/
#define DRR2  *((volatile unsigned int *)0x007800)  /* R 0x0000    McBSP Data Receive Register 2, */
                                                    /*            read First if the word size is greater than 16 bits,
                                                                  else ignore DRR2  */

#define DRR1  *((volatile unsigned int *)0x007801)  /* R 0x0000    McBSP Data Receive Register 1   */
                                                     /*            Read Second if the word size is greater than 16 bits,
                                                                   else read DRR1 only  */

#define DXR2  *((volatile unsigned int *)0x007802)  /* W 0x0000    McBSP Data Transmit Register 2    */
                                                    /*             Write First if the word size is greater than 16 bits,
                                                                    else ignore DXR2  */
#define DXR1  *((volatile unsigned int *)0x007803)  /* W 0x0000    McBSP Data Transmit Register 1    */
                                                    /*             Write Second if the word size is greater than 16 bits,
                                                                   else write to DXR1 only    */

  /*=================   McBSP CONTROL REGISTERS   ==============================*/
#define SPCR2 *((volatile unsigned int *)0x007804) /* R/W 0x0000    McBSP Serial Port Control Register 2  */
#define SPCR1 *((volatile unsigned int *)0x007805) /* R/W 0x0000    McBSP Serial Port Control Register 1  */
#define RCR2  *((volatile unsigned int *)0x007806) /* R/W 0x0000    McBSP Receive Control Register 2      */
#define RCR1  *((volatile unsigned int *)0x007807) /* R/W 0x0000    McBSP Receive Control Register 1      */
#define XCR2  *((volatile unsigned int *)0x007808) /* R/W 0x0000    McBSP Transmit Control Register 2     */
#define XCR1  *((volatile unsigned int *)0x007809) /* R/W 0x0000    McBSP Transmit Control Register 1     */
#define SRGR2 *((volatile unsigned int *)0x00780A) /* R/W 0x0000    McBSP Sample Rate Generator Register 2 */
#define SRGR1 *((volatile unsigned int *)0x00780B) /* R/W 0x0000    McBSP Sample Rate Generator Register 1 */

/*=====================  MULTICHANNEL CONTROL REGISTERS  ==========================================*/
#define MCR2    *((volatile unsigned int *)0x00780C) /* R/W 0x0000  McBSP Multichannel Register 2   */
#define MCR1    *((volatile unsigned int *)0x00780D) /* R/W 0x0000  McBSP Multichannel Register 1   */
#define RCERA   *((volatile unsigned int *)0x00780E) /* R/W 0x0000  McBSP Receive Channel Enable Register Partition A   */
#define RCERB   *((volatile unsigned int *)0x00780F) /* R/W 0x0000  McBSP Receive Channel Enable Register Partition B   */
#define XCERA   *((volatile unsigned int *)0x007810) /* R/W 0x0000  McBSP Transmit Channel Enable Register Partition A   */
#define XCERB   *((volatile unsigned int *)0x007811) /* R/W 0x0000 McBSP Transmit Channel Enable Register Partition B   */
#define PCR1    *((volatile unsigned int *)0x007812) /* R/W 0x0000 McBSP Pin Control Register   */
#define RCERC   *((volatile unsigned int *)0x007813) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition C   */
#define RCERD   *((volatile unsigned int *)0x007814) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition D   */
#define XCERC   *((volatile unsigned int *)0x007815) /* R/W 0x0000 McBSP Transmit Channel Enable Register Partition C   */
#define XCERD   *((volatile unsigned int *)0x007816) /* R/W 0x0000 McBSP Transmit Channel Enable Register   */


/*================== SCI-A Registers  =======================================*/

#define SCICCRA   *((volatile unsigned int *)0x007050)  /* 1 SCI-A Communications Control Register  */
#define SCICTL1A  *((volatile unsigned int *)0x007051)  /* 1 SCI-A Control Register 1  */
#define SCIHBAUDA *((volatile unsigned int *)0x007052)  /* 1 SCI-A Baud Register, High Bits  */
#define SCILBAUDA *((volatile unsigned int *)0x007053)  /* 1 SCI-A Baud Register, Low Bits  */
#define SCICTL2A  *((volatile unsigned int *)0x007054)  /* 1 SCI-A Control Register 2  */
#define SCIRXSTA  *((volatile unsigned int *)0x007055)  /* 1 SCI-A Receive Status Register  */
#define SCIRXEMUA *((volatile unsigned int *)0x007056)  /* 1 SCI-A Receive Emulation Data Buffer Register  */
#define SCIRXBUFA *((volatile unsigned int *)0x007057)  /* 1 SCI-A Receive Data Buffer Register  */
#define SCITXBUFA *((volatile unsigned int *)0x007059)  /* 1 SCI-A Transmit Data Buffer Register  */
#define SCIFFTXA  *((volatile unsigned int *)0x00705A)  /* 1 SCI-A FIFO Transmit Register  */
#define SCIFFRXA  *((volatile unsigned int *)0x00705B)  /* 1 SCI-A FIFO Receive Register  */
#define SCIFFCTA  *((volatile unsigned int *)0x00705C)  /* 1 SCI-A FIFO Control Register  */
#define SCIPRIA   *((volatile unsigned int *)0x00705F)  /* 1 SCI-A Priority Control Register  */

/*=================    SCI-B Registers  =====================================*/
#define SCICCRB   *((volatile unsigned int *)0x007750)  /* 1 SCI-B Communications Control Register  */
#define SCICTL1B  *((volatile unsigned int *)0x007751)  /* 1 SCI-B Control Register 1  */
#define SCIHBAUDB *((volatile unsigned int *)0x007752)  /* 1 SCI-B Baud Register, High Bits  */
#define SCILBAUDB *((volatile unsigned int *)0x007753)  /* 1 SCI-B Baud Register, Low Bits  */
#define SCICTL2B  *((volatile unsigned int *)0x007754)  /* 1 SCI-B Control Register 2  */
#define SCIRXSTB  *((volatile unsigned int *)0x007755)  /* 1 SCI-B Receive Status Register  */
#define SCIRXEMUB *((volatile unsigned int *)0x007756)  /* 1 SCI-B Receive Emulation Data Buffer Register  */
#define SCIRXBUFB *((volatile unsigned int *)0x007757)  /* 1 SCI-B Receive Data Buffer Register  */
#define SCITXBUFB *((volatile unsigned int *)0x007759)  /* 1 SCI-B Transmit Data Buffer Register  */
#define SCIFFTXB  *((volatile unsigned int *)0x00775A)  /* 1 SCI-B FIFO Transmit Register  */
#define SCIFFRXB  *((volatile unsigned int *)0x00775B)  /* 1 SCI-B FIFO Receive Register  */
#define SCIFFCTB  *((volatile unsigned int *)0x00775C)  /* 1 SCI-B FIFO Control Register  */
#define SCIPRIB   *((volatile unsigned int *)0x00775F)  /* 1 SCI-B Priority Control Register  */


/*====================   SPI Registers   ============================================*/
#define SPICCR   *((volatile unsigned int *)0x007040)  /* 1 SPI Configuration Control Register  */
#define SPICTL   *((volatile unsigned int *)0x007041)  /* 1 SPI Operation Control Register  */
#define SPISTS   *((volatile unsigned int *)0x007042)  /* 1 SPI Status Register  */
#define SPIBRR   *((volatile unsigned int *)0x007044)  /* 1 SPI Baud Rate Register  */
#define SPIRXEMU *((volatile unsigned int *)0x007046)  /* 1 SPI Receive Emulation Buffer Register  */
#define SPIRXBUF *((volatile unsigned int *)0x007047)  /* 1 SPI Serial Input Buffer Register  */
#define SPITXBUF *((volatile unsigned int *)0x007048)  /* 1 SPI Serial Output Buffer Register  */
#define SPIDAT   *((volatile unsigned int *)0x007049)  /* 1 SPI Serial Data Register  */
#define SPIFFTX  *((volatile unsigned int *)0x00704A)  /* 1 SPI FIFO Transmit Register  */
#define SPIFFRX  *((volatile unsigned int *)0x00704B)  /* 1 SPI FIFO Receive Register  */
#define SPIFFCT  *((volatile unsigned int *)0x00704C)  /* 1 SPI FIFO Control Register  */
#define SPIPRI   *((volatile unsigned int *)0x00704F)  /* 1 SPI Priority Control Register  */


/*==============   XINTF Configuration and Control Register Mappings   ===============*/
#define XTIMING0  *((volatile unsigned long *)0x000B20)  /* 2 XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register  */
#define XTIMING1  *((volatile unsigned long *)0x000B22)  /* 2 XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register  */
#define XTIMING2  *((volatile unsigned long *)0x000B24)  /* 2 XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register  */
#define XTIMING6  *((volatile unsigned long *)0x000B2C)  /* 2 XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register  */
#define XTIMING7  *((volatile unsigned long *)0x000B2E)  /* 2 XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register  */
#define XINTCNF2  *((volatile unsigned long *)0x000B34)  /* 2 XINTF Configuration Register can access as two 16-bit registers or one 32-bit register  */
#define XBANK      *((volatile unsigned int *)0x000B38)  /* 1 XINTF Bank Control Register  */
#define XREVISION  *((volatile unsigned int *)0x000B3A)  /* 1 XINTF Revision Register  */

/*==================  External Interrupts Registers  ============================*/
#define XINT1CR    *((volatile unsigned int *)0x007070)  /* 1 XINT1 control register  */
#define XINT2CR    *((volatile unsigned int *)0x007071)  /* 1 XINT2 control register  */

/*    reserved 0x00 7072 ~ 0x00 7076  5  */

#define XNMICR     *((volatile unsigned int *)0x007077)  /* 1 XNMI control register  */
#define XINT1CTR   *((volatile unsigned int *)0x007078)  /* 1 XINT1 counter register  */
#define XINT2CTR   *((volatile unsigned int *)0x007079)  /* 1 XINT2 counter register  */

/*   reserved 0x00 707A ~ 0x00 707E   5   */

#define XNMICTR    *((volatile unsigned int *)0x00707F)  /* 1 XNMI counter register  */

#endif