📄 f281x.h
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/*================= ADC Registers ==============================================*/
#define ADCTRL1 *((volatile unsigned int *)0x007100) /* 1 ADC Control Register 1 */
#define ADCTRL2 *((volatile unsigned int *)0x007101) /* 1 ADC Control Register 2 */
#define ADCMAXCONV *((volatile unsigned int *)0x007102) /* 1 ADC Maximum Conversion Channels Register */
#define ADCCHSELSEQ1 *((volatile unsigned int *)0x007103) /* 1 ADC Channel Select Sequencing Control Register 1 */
#define ADCCHSELSEQ2 *((volatile unsigned int *)0x007104) /* 1 ADC Channel Select Sequencing Control Register 2 */
#define ADCCHSELSEQ3 *((volatile unsigned int *)0x007105) /* 1 ADC Channel Select Sequencing Control Register 3 */
#define ADCCHSELSEQ4 *((volatile unsigned int *)0x007106) /* 1 ADC Channel Select Sequencing Control Register 4 */
#define ADCASEQSR *((volatile unsigned int *)0x007107) /* 1 ADC Auto-Sequence Status Register */
#define ADCRESULT0 *((volatile unsigned int *)0x007108) /* 1 ADC Conversion Result Buffer Register 0 */
#define ADCRESULT1 *((volatile unsigned int *)0x007109) /* 1 ADC Conversion Result Buffer Register 1 */
#define ADCRESULT2 *((volatile unsigned int *)0x00710A) /* 1 ADC Conversion Result Buffer Register 2 */
#define ADCRESULT3 *((volatile unsigned int *)0x00710B) /* 1 ADC Conversion Result Buffer Register 3 */
#define ADCRESULT4 *((volatile unsigned int *)0x00710C) /* 1 ADC Conversion Result Buffer Register 4 */
#define ADCRESULT5 *((volatile unsigned int *)0x00710D) /* 1 ADC Conversion Result Buffer Register 5 */
#define ADCRESULT6 *((volatile unsigned int *)0x00710E) /* 1 ADC Conversion Result Buffer Register 6 */
#define ADCRESULT7 *((volatile unsigned int *)0x00710F) /* 1 ADC Conversion Result Buffer Register 7 */
#define ADCRESULT8 *((volatile unsigned int *)0x007110) /* 1 ADC Conversion Result Buffer Register 8 */
#define ADCRESULT9 *((volatile unsigned int *)0x007111) /* 1 ADC Conversion Result Buffer Register 9 */
#define ADCRESULT10 *((volatile unsigned int *)0x007112) /* 1 ADC Conversion Result Buffer Register 10 */
#define ADCRESULT11 *((volatile unsigned int *)0x007113) /* 1 ADC Conversion Result Buffer Register 11 */
#define ADCRESULT12 *((volatile unsigned int *)0x007114) /* 1 ADC Conversion Result Buffer Register 12 */
#define ADCRESULT13 *((volatile unsigned int *)0x007115) /* 1 ADC Conversion Result Buffer Register 13 */
#define ADCRESULT14 *((volatile unsigned int *)0x007116) /* 1 ADC Conversion Result Buffer Register 14 */
#define ADCRESULT15 *((volatile unsigned int *)0x007117) /* 1 ADC Conversion Result Buffer Register 15 */
#define ADCTRL3 *((volatile unsigned int *)0x007118) /* 1 ADC Control Register 3 */
#define ADCST *((volatile unsigned int *)0x007119) /* 1 ADC Status Register */
/* reserved 0x00711C ~ 0x00 711F 4 Words */
/*======================= Device Emulation Registers ================================*/
#define DEVICECNF *((volatile unsigned long *)0x000880) /* 2 Device Configuration Register */
/* reserved 0x00 0882 1 Not supported on Revision C and later silicon */
#define DEVICEID *((volatile unsigned int *)0x000883) /* 1 Device ID Register */
#define PROTSTART *((volatile unsigned int *)0x000884) /* 1 Block Protection Start Address Register */
#define PROTRANGE *((volatile unsigned int *)0x000885) /* 1 Block Protection Range Address Register */
/* reserved 0x000886 ~ 0x0009FF 378 Words */
/*===================== eCAN Registers Map ===========================*/
#define CANME *((volatile unsigned long *)0x006000) /* 1 Mailbox enable */
#define CANMD *((volatile unsigned long *)0x006002) /* 1 Mailbox direction */
#define CANTRS *((volatile unsigned long *)0x006004) /* 1 Transmit request set */
#define CANTRR *((volatile unsigned long *)0x006006) /* 1 Transmit request reset */
#define CANTA *((volatile unsigned long *)0x006008) /* 1 Transmission acknowledge */
#define CANAA *((volatile unsigned long *)0x00600A) /* 1 Abort acknowledge */
#define CANRMP *((volatile unsigned long *)0x00600C) /* 1 Receive message pending */
#define CANRML *((volatile unsigned long *)0x00600E) /* 1 Receive message lost */
#define CANRFP *((volatile unsigned long *)0x006010) /* 1 Remote frame pending */
#define CANGAM *((volatile unsigned long *)0x006012) /* 1 Global acceptance mask */
#define CANMC *((volatile unsigned long *)0x006014) /* 1 Master control */
#define CANBTC *((volatile unsigned long *)0x006016) /* 1 Bit-timing configuration */
#define CANES *((volatile unsigned long *)0x006018) /* 1 Error and status */
#define CANTEC *((volatile unsigned long *)0x00601A) /* 1 Transmit error counter */
#define CANREC *((volatile unsigned long *)0x00601C) /* 1 Receive error counter */
#define CANGIF0 *((volatile unsigned long *)0x00601E) /* 1 Global interrupt flag 0 */
#define CANGIM *((volatile unsigned long *)0x006020) /* 1 Global interrupt mask */
#define CANGIF1 *((volatile unsigned long *)0x006022) /* 1 Global interrupt flag 1 */
#define CANMIM *((volatile unsigned long *)0x006024) /* 1 Mailbox interrupt mask */
#define CANMIL *((volatile unsigned long *)0x006026) /* 1 Mailbox interrupt level */
#define CANOPC *((volatile unsigned long *)0x006028) /* 1 Overwrite protection control */
#define CANTIOC *((volatile unsigned long *)0x00602A) /* 1 TX I/O control */
#define CANRIOC *((volatile unsigned long *)0x00602C) /* 1 RX I/O control */
#define CANLNT *((volatile unsigned long *)0x00602E) /* 1 Local network time (Reserved in SCC mode) */
#define CANTOC *((volatile unsigned long *)0x006030) /* 1 Time-out control (Reserved in SCC mode) */
#define CANTOS *((volatile unsigned long *)0x006032) /* 1 Time-out status (Reserved in SCC mode) */
/* reserved 0x006033 ~ 0x006fff Words */
/*=================== EVA Registers NAME ADDRESS ===================*/
#define GPTCONA *((volatile unsigned int *)0x007400) /* 1 GP Timer Control Register A */
#define T1CNT *((volatile unsigned int *)0x007401) /* 1 GP Timer 1 Counter Register */
#define T1CMPR *((volatile unsigned int *)0x007402) /* 1 GP Timer 1 Compare Register */
#define T1PR *((volatile unsigned int *)0x007403) /* 1 GP Timer 1 Period Register */
#define T1CON *((volatile unsigned int *)0x007404) /* 1 GP Timer 1 Control Register */
#define T2CNT *((volatile unsigned int *)0x007405) /* 1 GP Timer 2 Counter Register */
#define T2CMPR *((volatile unsigned int *)0x007406) /* 1 GP Timer 2 Compare Register */
#define T2PR *((volatile unsigned int *)0x007407) /* 1 GP Timer 2 Period Register */
#define T2CON *((volatile unsigned int *)0x007408) /* 1 GP Timer 2 Control Register */
#define EXTCONA *((volatile unsigned int *)0x007409) /* 1 GP Extension Control Register A */
#define COMCONA *((volatile unsigned int *)0x007411) /* 1 Compare Control Register A */
#define ACTRA *((volatile unsigned int *)0x007413) /* 1 Compare Action Control Register A */
#define DBTCONA *((volatile unsigned int *)0x007415) /* 1 Dead-Band Timer Control Register A */
#define CMPR1 *((volatile unsigned int *)0x007417) /* 1 Compare Register 1 */
#define CMPR2 *((volatile unsigned int *)0x007418) /* 1 Compare Register 2 */
#define CMPR3 *((volatile unsigned int *)0x007419) /* 1 Compare Register 3 */
#define CAPCONA *((volatile unsigned int *)0x007420) /* 1 Capture Control Register A */
#define CAPFIFOA *((volatile unsigned int *)0x007422) /* 1 Capture FIFO Status Register A */
#define CAP1FIFO *((volatile unsigned int *)0x007423) /* 1 Two-Level Deep Capture FIFO Stack 1 */
#define CAP2FIFO *((volatile unsigned int *)0x007424) /* 1 Two-Level Deep Capture FIFO Stack 2 */
#define CAP3FIFO *((volatile unsigned int *)0x007425) /* 1 Two-Level Deep Capture FIFO Stack 3 */
#define CAP1FBOT *((volatile unsigned int *)0x007427) /* 1 Bottom Register Of Capture FIFO Stack 1 */
#define CAP2FBOT *((volatile unsigned int *)0x007428) /* 1 Bottom Register Of Capture FIFO Stack 2 */
#define CAP3FBOT *((volatile unsigned int *)0x007429) /* 1 Bottom Register Of Capture FIFO Stack 3 */
#define EVAIMRA *((volatile unsigned int *)0x00742C) /* 1 Interrupt Mask Register A */
#define EVAIMRB *((volatile unsigned int *)0x00742D) /* 1 Interrupt Mask Register B */
#define EVAIMRC *((volatile unsigned int *)0x00742E) /* 1 Interrupt Mask Register C */
#define EVAIFRA *((volatile unsigned int *)0x00742F) /* 1 Interrupt Flag Register A */
#define EVAIFRB *((volatile unsigned int *)0x007430) /* 1 Interrupt Flag Register B */
#define EVAIFRC *((volatile unsigned int *)0x007431) /* 1 Interrupt Flag Register C */
/* reserved 0x007432 ~ 0x00743F */
/*=================== EVB Registers NAME ADDRESS ===================*/
#define GPTCONB *((volatile unsigned int *)0x007500) /* 1 GP Timer Control Register b */
#define T3CNT *((volatile unsigned int *)0x007501) /* 1 GP Timer 3 Counter Register */
#define T3CMPR *((volatile unsigned int *)0x007502) /* 1 GP Timer 3 Compare Register */
#define T3PR *((volatile unsigned int *)0x007503) /* 1 GP Timer 3 Period Register */
#define T3CON *((volatile unsigned int *)0x007504) /* 1 GP Timer 3 Control Register */
#define T4CNT *((volatile unsigned int *)0x007505) /* 1 GP Timer 4 Counter Register */
#define T4CMPR *((volatile unsigned int *)0x007506) /* 1 GP Timer 4 Compare Register */
#define T4PR *((volatile unsigned int *)0x007507) /* 1 GP Timer 4 Period Register */
#define T4CON *((volatile unsigned int *)0x007508) /* 1 GP Timer 4 Control Register */
#define EXTCONB *((volatile unsigned int *)0x007509) /* 1 GP Extension Control Register B */
#define COMCONB *((volatile unsigned int *)0x007511) /* 1 Compare Control Register B */
#define ACTRB *((volatile unsigned int *)0x007513) /* 1 Compare Action Control Register B */
#define DBTCONB *((volatile unsigned int *)0x007515) /* 1 Dead-Band Timer Control Register B */
#define CMPR4 *((volatile unsigned int *)0x007517) /* 1 Compare Register 4 */
#define CMPR5 *((volatile unsigned int *)0x007518) /* 1 Compare Register 5 */
#define CMPR6 *((volatile unsigned int *)0x007519) /* 1 Compare Register 6 */
#define CAPCONB *((volatile unsigned int *)0x007520) /* 1 Capture Control Register B */
#define CAPFIFOB *((volatile unsigned int *)0x007522) /* 1 Capture FIFO Status Register B */
#define CAP4FIFO *((volatile unsigned int *)0x007523) /* 1 Two-Level Deep Capture FIFO Stack 4 */
#define CAP5FIFO *((volatile unsigned int *)0x007524) /* 1 Two-Level Deep Capture FIFO Stack 5 */
#define CAP6FIFO *((volatile unsigned int *)0x007525) /* 1 Two-Level Deep Capture FIFO Stack 6 */
#define CAP4FBOT *((volatile unsigned int *)0x007527) /* 1 Bottom Register Of Capture FIFO Stack 4 */
#define CAP5FBOT *((volatile unsigned int *)0x007528) /* 1 Bottom Register Of Capture FIFO Stack 5 */
#define CAP6FBOT *((volatile unsigned int *)0x007529) /* 1 Bottom Register Of Capture FIFO Stack 6 */
#define EVBIMRA *((volatile unsigned int *)0x00752C) /* 1 Interrupt Mask Register A */
#define EVBIMRB *((volatile unsigned int *)0x00752D) /* 1 Interrupt Mask Register B */
#define EVBIMRC *((volatile unsigned int *)0x00752E) /* 1 Interrupt Mask Register C */
#define EVBIFRA *((volatile unsigned int *)0x00752F) /* 1 Interrupt Flag Register A */
#define EVBIFRB *((volatile unsigned int *)0x007530) /* 1 Interrupt Flag Register B */
#define EVBIFRC *((volatile unsigned int *)0x007531) /* 1 Interrupt Flag Register C */
/* reserved 0x007532 ~ 0x00753F */
/*====================== GPIO Mux Registers =========================*/
#define GPAMUX *((volatile unsigned int *)0x0070C0) /* 1 GPIO A Mux Control Register */
#define GPADIR *((volatile unsigned int *)0x0070C1) /* 1 GPIO A Direction Control Register */
#define GPAQUAL *((volatile unsigned int *)0x0070C2) /* 1 GPIO A Input Qualification Control Register */
/* reserved 0x00 70C3 1 */
#define GPBMUX *((volatile unsigned int *)0x0070C4) /* 1 GPIO B Mux Control Register */
#define GPBDIR *((volatile unsigned int *)0x0070C5) /* 1 GPIO B Direction Control Register */
#define GPBQUAL *((volatile unsigned int *)0x0070C6) /* 1 GPIO B Input Qualification Control Register */
/* reserved 0x00 70C7 1 */
/* reserved 0x00 70C8 1 */
/* reserved 0x00 70C9 1 */
/* reserved 0x00 70CA 1 */
/* reserved 0x00 70CB 1 */
#define GPDMUX *((volatile unsigned int *)0x0070CC) /* 1 GPIO D Mux Control Register */
#define GPDDIR *((volatile unsigned int *)0x0070CD) /* 1 GPIO D Direction Control Register */
#define GPDQUAL *((volatile unsigned int *)0x0070CE) /* 1 GPIO D Input Qualification Control Register */
/* reserved 0x00 70CF 1 */
#define GPEMUX *((volatile unsigned int *)0x0070D0) /* 1 GPIO E Mux Control Register */
#define GPEDIR *((volatile unsigned int *)0x0070D1) /* 1 GPIO E Direction Control Register */
#define GPEQUAL *((volatile unsigned int *)0x0070D2) /* 1 GPIO E Input Qualification Control Register */
/* reserved 0x00 70D3 1 */
#define GPFMUX *((volatile unsigned int *)0x0070D4) /* 1 GPIO F Mux Control Register */
#define GPFDIR *((volatile unsigned int *)0x0070D5) /* 1 GPIO F Direction Control Register */
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