edata_reg_risc_selectunit.vhd

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 LIBRARY ieee; 
 use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
 use ieee.std_logic_arith.all; 
 use ieee.std_logic_unsigned.all;



entity EDATA_REG_RISC_SelectUnit is
port (		
	RESET_L                                                 : in std_logic;
	RESET_FRAME_L                                           : in std_logic;
	CK_MP                                                   : in std_logic;
	RH_WL                                                   : in std_logic;
	EXEC                                                    : in std_logic;
	OP_DONE                                                 : out std_logic;
	ADDRESS                                                 : in std_logic_vector(7 downto 0);
	WR_DATA                                                 : in std_logic_vector(7 downto 0);
	RD_DATA                                                 : out std_logic_vector(7 downto 0);
	RD_BIT_0x0_0                                            : in std_logic;
	WRITE_EN_PIN_0x0                                        : out std_logic;
	RD_BIT_0x1_0                                            : in std_logic;
	WRITE_EN_PIN_0x1                                        : out std_logic;
	RD_BIT_0x2_0                                            : in std_logic;
	WRITE_EN_PIN_0x2                                        : out std_logic;
	RD_BIT_0x3_0                                            : in std_logic;
	WRITE_EN_PIN_0x3                                        : out std_logic;
	RD_BIT_0x4_0                                            : in std_logic;
	WRITE_EN_PIN_0x4                                        : out std_logic;
	RD_BIT_0x5_0                                            : in std_logic;
	WRITE_EN_PIN_0x5                                        : out std_logic;
	RD_BIT_0x6_0                                            : in std_logic;
	WRITE_EN_PIN_0x6                                        : out std_logic;
	RD_BIT_0x7_0                                            : in std_logic;
	WRITE_EN_PIN_0x7                                        : out std_logic;
	RD_BIT_0x8_0                                            : in std_logic;
	RD_BIT_0x9_1                                            : in std_logic;
	RD_BIT_0xa_2                                            : in std_logic;
	RD_BIT_0xb_3                                            : in std_logic;
	RD_BIT_0xc_4                                            : in std_logic;
	RD_BIT_0xd_5                                            : in std_logic;
	RD_BIT_0xe_6                                            : in std_logic;
	RD_BIT_0xf_7                                            : in std_logic;
	RD_BIT_0x10_0                                           : in std_logic;
	WRITE_EN_PIN_0x10                                       : out std_logic;
	RD_BIT_0x11_0                                           : in std_logic;
	WRITE_EN_PIN_0x11                                       : out std_logic;
	RD_BIT_0x12_0                                           : in std_logic;
	WRITE_EN_PIN_0x12                                       : out std_logic;
	RD_BIT_0x13_0                                           : in std_logic;
	RD_BIT_0x14_0                                           : in std_logic;
	RD_BIT_0x14_1                                           : in std_logic;
	RD_BIT_0x14_2                                           : in std_logic;
	RD_BIT_0x15_0                                           : in std_logic;
	WRITE_EN_PIN_0x15                                       : out std_logic
);
end EDATA_REG_RISC_SelectUnit;
architecture BEHAVIORAL of EDATA_REG_RISC_SelectUnit is
signal SELECT_EN_0x0:std_logic;
signal SELECT_EN_0x1:std_logic;
signal SELECT_EN_0x2:std_logic;
signal SELECT_EN_0x3:std_logic;
signal SELECT_EN_0x4:std_logic;
signal SELECT_EN_0x5:std_logic;
signal SELECT_EN_0x6:std_logic;
signal SELECT_EN_0x7:std_logic;
signal SELECT_EN_0x8:std_logic;
signal SELECT_EN_0x9:std_logic;
signal SELECT_EN_0xa:std_logic;
signal SELECT_EN_0xb:std_logic;
signal SELECT_EN_0xc:std_logic;
signal SELECT_EN_0xd:std_logic;
signal SELECT_EN_0xe:std_logic;
signal SELECT_EN_0xf:std_logic;
signal SELECT_EN_0x10:std_logic;
signal SELECT_EN_0x11:std_logic;
signal SELECT_EN_0x12:std_logic;
signal SELECT_EN_0x13:std_logic;
signal SELECT_EN_0x14:std_logic;
signal SELECT_EN_0x15:std_logic;
signal SELF_EXEC:std_logic;
signal SELF_OP_DONE:std_logic;
signal SELF_EN:std_logic;
signal READ:std_logic;
signal WRITE:std_logic;
signal READ_CLEAR:std_logic;
begin

	SELECT_EN_0x0 <= '1' when (ADDRESS ="00000000") else '0';
	SELECT_EN_0x1 <= '1' when (ADDRESS ="00000001") else '0';
	SELECT_EN_0x2 <= '1' when (ADDRESS ="00000010") else '0';
	SELECT_EN_0x3 <= '1' when (ADDRESS ="00000011") else '0';
	SELECT_EN_0x4 <= '1' when (ADDRESS ="00000100") else '0';
	SELECT_EN_0x5 <= '1' when (ADDRESS ="00000101") else '0';
	SELECT_EN_0x6 <= '1' when (ADDRESS ="00000110") else '0';
	SELECT_EN_0x7 <= '1' when (ADDRESS ="00000111") else '0';
	SELECT_EN_0x8 <= '1' when (ADDRESS ="00001000") else '0';
	SELECT_EN_0x9 <= '1' when (ADDRESS ="00001001") else '0';
	SELECT_EN_0xa <= '1' when (ADDRESS ="00001010") else '0';
	SELECT_EN_0xb <= '1' when (ADDRESS ="00001011") else '0';
	SELECT_EN_0xc <= '1' when (ADDRESS ="00001100") else '0';
	SELECT_EN_0xd <= '1' when (ADDRESS ="00001101") else '0';
	SELECT_EN_0xe <= '1' when (ADDRESS ="00001110") else '0';
	SELECT_EN_0xf <= '1' when (ADDRESS ="00001111") else '0';
	SELECT_EN_0x10 <= '1' when (ADDRESS ="00010000") else '0';
	SELECT_EN_0x11 <= '1' when (ADDRESS ="00010001") else '0';
	SELECT_EN_0x12 <= '1' when (ADDRESS ="00010010") else '0';
	SELECT_EN_0x13 <= '1' when (ADDRESS ="00010011") else '0';
	SELECT_EN_0x14 <= '1' when (ADDRESS ="00010100") else '0';
	SELECT_EN_0x15 <= '1' when (ADDRESS ="00010101") else '0';
	SELF_EN<='1';

	SELF_EXEC<=EXEC and SELF_EN;

	Process(CK_MP,RESET_FRAME_L)
	begin
		if(RESET_FRAME_L='0') then
			SELF_OP_DONE<='0';
			READ_CLEAR<='0';
		else
			If(CK_MP'event and CK_MP='1') then
				SELF_OP_DONE<=SELF_EXEC and SELF_EN;
				READ_CLEAR<=SELF_EXEC and SELF_EN and READ;
			end if;
		end if;
	end process;

	OP_DONE<=(SELF_OP_DONE and SELF_EN) ;

	READ<=RH_WL;
	WRITE<= (not RH_WL) and EXEC;

	WRITE_EN_PIN_0x0<=WRITE and SELECT_EN_0x0;
	WRITE_EN_PIN_0x1<=WRITE and SELECT_EN_0x1;
	WRITE_EN_PIN_0x2<=WRITE and SELECT_EN_0x2;
	WRITE_EN_PIN_0x3<=WRITE and SELECT_EN_0x3;
	WRITE_EN_PIN_0x4<=WRITE and SELECT_EN_0x4;
	WRITE_EN_PIN_0x5<=WRITE and SELECT_EN_0x5;
	WRITE_EN_PIN_0x6<=WRITE and SELECT_EN_0x6;
	WRITE_EN_PIN_0x7<=WRITE and SELECT_EN_0x7;
	WRITE_EN_PIN_0x10<=WRITE and SELECT_EN_0x10;
	WRITE_EN_PIN_0x11<=WRITE and SELECT_EN_0x11;
	WRITE_EN_PIN_0x12<=WRITE and SELECT_EN_0x12;
	WRITE_EN_PIN_0x15<=WRITE and SELECT_EN_0x15;

	RD_DATA(0)<='0'
		 or (RD_BIT_0x0_0 and SELECT_EN_0x0)
		 or (RD_BIT_0x1_0 and SELECT_EN_0x1)
		 or (RD_BIT_0x2_0 and SELECT_EN_0x2)
		 or (RD_BIT_0x3_0 and SELECT_EN_0x3)
		 or (RD_BIT_0x4_0 and SELECT_EN_0x4)
		 or (RD_BIT_0x5_0 and SELECT_EN_0x5)
		 or (RD_BIT_0x6_0 and SELECT_EN_0x6)
		 or (RD_BIT_0x7_0 and SELECT_EN_0x7)
		 or (RD_BIT_0x8_0 and SELECT_EN_0x8)
		 or (RD_BIT_0x10_0 and SELECT_EN_0x10)
		 or (RD_BIT_0x11_0 and SELECT_EN_0x11)
		 or (RD_BIT_0x12_0 and SELECT_EN_0x12)
		 or (RD_BIT_0x13_0 and SELECT_EN_0x13)
		 or (RD_BIT_0x14_0 and SELECT_EN_0x14)
		 or (RD_BIT_0x15_0 and SELECT_EN_0x15);

	RD_DATA(1)<='0'
		 or (RD_BIT_0x9_1 and SELECT_EN_0x9)
		 or (RD_BIT_0x14_1 and SELECT_EN_0x14);

	RD_DATA(2)<='0'
		 or (RD_BIT_0xa_2 and SELECT_EN_0xa)
		 or (RD_BIT_0x14_2 and SELECT_EN_0x14);

	RD_DATA(3)<='0'
		 or (RD_BIT_0xb_3 and SELECT_EN_0xb);

	RD_DATA(4)<='0'
		 or (RD_BIT_0xc_4 and SELECT_EN_0xc);

	RD_DATA(5)<='0'
		 or (RD_BIT_0xd_5 and SELECT_EN_0xd);

	RD_DATA(6)<='0'
		 or (RD_BIT_0xe_6 and SELECT_EN_0xe);

	RD_DATA(7)<='0'
		 or (RD_BIT_0xf_7 and SELECT_EN_0xf);


end BEHAVIORAL;