edata_reg_risc_readonly.vhd

vhdl语言,用专门的工具产生的这个文件

 LIBRARY ieee; 
 use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
 use ieee.std_logic_arith.all; 
 use ieee.std_logic_unsigned.all;



entity EDATA_REG_RISC_ReadOnly is
port (		
	SPEED_MONITOR_0                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_1                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_2                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_3                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_4                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_5                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_6                                         : in std_logic_vector(0 downto 0);
	SPEED_MONITOR_7                                         : in std_logic_vector(0 downto 0);
	SPI_DI                                                  : in std_logic_vector(0 downto 0);
	MODE                                                    : in std_logic_vector(2 downto 0);
	RD_BIT_0x8_0                                            : out std_logic;
	RD_BIT_0x9_1                                            : out std_logic;
	RD_BIT_0xa_2                                            : out std_logic;
	RD_BIT_0xb_3                                            : out std_logic;
	RD_BIT_0xc_4                                            : out std_logic;
	RD_BIT_0xd_5                                            : out std_logic;
	RD_BIT_0xe_6                                            : out std_logic;
	RD_BIT_0xf_7                                            : out std_logic;
	RD_BIT_0x13_0                                           : out std_logic;
	RD_BIT_0x14_0                                           : out std_logic;
	RD_BIT_0x14_1                                           : out std_logic;
	RD_BIT_0x14_2                                           : out std_logic
);
end EDATA_REG_RISC_ReadOnly;
architecture BEHAVIORAL of EDATA_REG_RISC_ReadOnly is
begin

	RD_BIT_0x8_0<=SPEED_MONITOR_0(0);
	RD_BIT_0x9_1<=SPEED_MONITOR_1(0);
	RD_BIT_0xa_2<=SPEED_MONITOR_2(0);
	RD_BIT_0xb_3<=SPEED_MONITOR_3(0);
	RD_BIT_0xc_4<=SPEED_MONITOR_4(0);
	RD_BIT_0xd_5<=SPEED_MONITOR_5(0);
	RD_BIT_0xe_6<=SPEED_MONITOR_6(0);
	RD_BIT_0xf_7<=SPEED_MONITOR_7(0);
	RD_BIT_0x13_0<=SPI_DI(0);
	RD_BIT_0x14_0<=MODE(0);
	RD_BIT_0x14_1<=MODE(1);
	RD_BIT_0x14_2<=MODE(2);

end BEHAVIORAL;