edata_reg_risc_writeread.vhd

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 LIBRARY ieee; 
 use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
 use ieee.std_logic_arith.all; 
 use ieee.std_logic_unsigned.all;



entity EDATA_REG_RISC_WriteRead is
port (		
	FAN_SPEED0                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED1                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED2                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED3                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED4                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED5                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED6                                              : out std_logic_vector(0 downto 0);
	FAN_SPEED7                                              : out std_logic_vector(0 downto 0);
	SPI_CLK                                                 : out std_logic_vector(0 downto 0);
	SPI_CE                                                  : out std_logic_vector(0 downto 0);
	SPI_DO                                                  : out std_logic_vector(0 downto 0);
	POWER_CTL                                               : out std_logic_vector(0 downto 0);
	CK_MP                                                   : in std_logic;
	RESET_L                                                 : in std_logic;
	WR_DATA                                                 : in std_logic_vector(7 downto 0);
	WRITE_EN_PIN_0x0                                        : in std_logic;
	RD_BIT_0x0_0                                            : out std_logic;
	WRITE_EN_PIN_0x1                                        : in std_logic;
	RD_BIT_0x1_0                                            : out std_logic;
	WRITE_EN_PIN_0x2                                        : in std_logic;
	RD_BIT_0x2_0                                            : out std_logic;
	WRITE_EN_PIN_0x3                                        : in std_logic;
	RD_BIT_0x3_0                                            : out std_logic;
	WRITE_EN_PIN_0x4                                        : in std_logic;
	RD_BIT_0x4_0                                            : out std_logic;
	WRITE_EN_PIN_0x5                                        : in std_logic;
	RD_BIT_0x5_0                                            : out std_logic;
	WRITE_EN_PIN_0x6                                        : in std_logic;
	RD_BIT_0x6_0                                            : out std_logic;
	WRITE_EN_PIN_0x7                                        : in std_logic;
	RD_BIT_0x7_0                                            : out std_logic;
	WRITE_EN_PIN_0x10                                       : in std_logic;
	RD_BIT_0x10_0                                           : out std_logic;
	WRITE_EN_PIN_0x11                                       : in std_logic;
	RD_BIT_0x11_0                                           : out std_logic;
	WRITE_EN_PIN_0x12                                       : in std_logic;
	RD_BIT_0x12_0                                           : out std_logic;
	WRITE_EN_PIN_0x15                                       : in std_logic;
	RD_BIT_0x15_0                                           : out std_logic
);
end EDATA_REG_RISC_WriteRead;
architecture BEHAVIORAL of EDATA_REG_RISC_WriteRead is
signal FAN_SPEED0_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED1_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED2_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED3_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED4_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED5_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED6_S                                            :  std_logic_vector(0 downto 0);
signal FAN_SPEED7_S                                            :  std_logic_vector(0 downto 0);
signal SPI_CLK_S                                               :  std_logic_vector(0 downto 0);
signal SPI_CE_S                                                :  std_logic_vector(0 downto 0);
signal SPI_DO_S                                                :  std_logic_vector(0 downto 0);
signal POWER_CTL_S                                             :  std_logic_vector(0 downto 0);
begin

	FAN_SPEED0<=FAN_SPEED0_S;
	FAN_SPEED1<=FAN_SPEED1_S;
	FAN_SPEED2<=FAN_SPEED2_S;
	FAN_SPEED3<=FAN_SPEED3_S;
	FAN_SPEED4<=FAN_SPEED4_S;
	FAN_SPEED5<=FAN_SPEED5_S;
	FAN_SPEED6<=FAN_SPEED6_S;
	FAN_SPEED7<=FAN_SPEED7_S;
	SPI_CLK<=SPI_CLK_S;
	SPI_CE<=SPI_CE_S;
	SPI_DO<=SPI_DO_S;
	POWER_CTL<=POWER_CTL_S;

	RD_BIT_0x0_0<=FAN_SPEED0_S(0);
	RD_BIT_0x1_0<=FAN_SPEED1_S(0);
	RD_BIT_0x2_0<=FAN_SPEED2_S(0);
	RD_BIT_0x3_0<=FAN_SPEED3_S(0);
	RD_BIT_0x4_0<=FAN_SPEED4_S(0);
	RD_BIT_0x5_0<=FAN_SPEED5_S(0);
	RD_BIT_0x6_0<=FAN_SPEED6_S(0);
	RD_BIT_0x7_0<=FAN_SPEED7_S(0);
	RD_BIT_0x10_0<=SPI_CLK_S(0);
	RD_BIT_0x11_0<=SPI_CE_S(0);
	RD_BIT_0x12_0<=SPI_DO_S(0);
	RD_BIT_0x15_0<=POWER_CTL_S(0);

	process(RESET_L,CK_MP)
	begin
		if(RESET_L='0') then
			FAN_SPEED0_S(0)<='0';
			FAN_SPEED1_S(0)<='0';
			FAN_SPEED2_S(0)<='0';
			FAN_SPEED3_S(0)<='0';
			FAN_SPEED4_S(0)<='0';
			FAN_SPEED5_S(0)<='0';
			FAN_SPEED6_S(0)<='0';
			FAN_SPEED7_S(0)<='0';
			SPI_CLK_S(0)<='0';
			SPI_CE_S(0)<='0';
			SPI_DO_S(0)<='0';
			POWER_CTL_S(0)<='0';
		else
			if(CK_MP'event and CK_MP='1') then
				if(WRITE_EN_PIN_0x0='1') then
					FAN_SPEED0_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x1='1') then
					FAN_SPEED1_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x2='1') then
					FAN_SPEED2_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x3='1') then
					FAN_SPEED3_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x4='1') then
					FAN_SPEED4_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x5='1') then
					FAN_SPEED5_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x6='1') then
					FAN_SPEED6_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x7='1') then
					FAN_SPEED7_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x10='1') then
					SPI_CLK_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x11='1') then
					SPI_CE_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x12='1') then
					SPI_DO_S(0)<=WR_DATA(0);
				end if;

				if(WRITE_EN_PIN_0x15='1') then
					POWER_CTL_S(0)<=WR_DATA(0);
				end if;

			end if;
		end if;
	end process;

end BEHAVIORAL;