edata_reg_risc.vhd

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signal RD_BIT_0xb_3                                            :  std_logic;
signal RD_BIT_0xc_4                                            :  std_logic;
signal RD_BIT_0xd_5                                            :  std_logic;
signal RD_BIT_0xe_6                                            :  std_logic;
signal RD_BIT_0xf_7                                            :  std_logic;
signal RD_BIT_0x10_0                                           :  std_logic;
signal WRITE_EN_PIN_0x10                                       :  std_logic;
signal RD_BIT_0x11_0                                           :  std_logic;
signal WRITE_EN_PIN_0x11                                       :  std_logic;
signal RD_BIT_0x12_0                                           :  std_logic;
signal WRITE_EN_PIN_0x12                                       :  std_logic;
signal RD_BIT_0x13_0                                           :  std_logic;
signal RD_BIT_0x14_0                                           :  std_logic;
signal RD_BIT_0x14_1                                           :  std_logic;
signal RD_BIT_0x14_2                                           :  std_logic;
signal RD_BIT_0x15_0                                           :  std_logic;
signal WRITE_EN_PIN_0x15                                       :  std_logic;
signal FAN_SPEED0_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED1_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED2_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED3_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED4_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED5_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED6_S_S_S                                        :  std_logic_vector(0 downto 0);
signal FAN_SPEED7_S_S_S                                        :  std_logic_vector(0 downto 0);
signal SPI_CLK_S_S_S                                           :  std_logic_vector(0 downto 0);
signal SPI_CE_S_S_S                                            :  std_logic_vector(0 downto 0);
signal SPI_DO_S_S_S                                            :  std_logic_vector(0 downto 0);
signal POWER_CTL_S_S_S                                         :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_0_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_1_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_2_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_3_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_4_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_5_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_6_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPEED_MONITOR_7_S_S_S                                   :  std_logic_vector(0 downto 0);
signal SPI_DI_S_S_S                                            :  std_logic_vector(0 downto 0);
begin

	FAN_SPEED0<=FAN_SPEED0_S_S_S(0);
	FAN_SPEED1<=FAN_SPEED1_S_S_S(0);
	FAN_SPEED2<=FAN_SPEED2_S_S_S(0);
	FAN_SPEED3<=FAN_SPEED3_S_S_S(0);
	FAN_SPEED4<=FAN_SPEED4_S_S_S(0);
	FAN_SPEED5<=FAN_SPEED5_S_S_S(0);
	FAN_SPEED6<=FAN_SPEED6_S_S_S(0);
	FAN_SPEED7<=FAN_SPEED7_S_S_S(0);
	SPI_CLK<=SPI_CLK_S_S_S(0);
	SPI_CE<=SPI_CE_S_S_S(0);
	SPI_DO<=SPI_DO_S_S_S(0);
	POWER_CTL<=POWER_CTL_S_S_S(0);
	SPEED_MONITOR_0_S_S_S(0)<=SPEED_MONITOR_0;
	SPEED_MONITOR_1_S_S_S(0)<=SPEED_MONITOR_1;
	SPEED_MONITOR_2_S_S_S(0)<=SPEED_MONITOR_2;
	SPEED_MONITOR_3_S_S_S(0)<=SPEED_MONITOR_3;
	SPEED_MONITOR_4_S_S_S(0)<=SPEED_MONITOR_4;
	SPEED_MONITOR_5_S_S_S(0)<=SPEED_MONITOR_5;
	SPEED_MONITOR_6_S_S_S(0)<=SPEED_MONITOR_6;
	SPEED_MONITOR_7_S_S_S(0)<=SPEED_MONITOR_7;
	SPI_DI_S_S_S(0)<=SPI_DI;

U1:
 EDATA_REG_RISC_SelectUnit port map(		
	RESET_L => RESET_L,
	RESET_FRAME_L => RESET_FRAME_L,
	CK_MP => CK_MP,
	RH_WL => RH_WL,
	EXEC => EXEC,
	OP_DONE => OP_DONE,
	ADDRESS => ADDRESS,
	WR_DATA => WR_DATA,
	RD_DATA => RD_DATA,
	RD_BIT_0x0_0 => RD_BIT_0x0_0,
	WRITE_EN_PIN_0x0 => WRITE_EN_PIN_0x0,
	RD_BIT_0x1_0 => RD_BIT_0x1_0,
	WRITE_EN_PIN_0x1 => WRITE_EN_PIN_0x1,
	RD_BIT_0x2_0 => RD_BIT_0x2_0,
	WRITE_EN_PIN_0x2 => WRITE_EN_PIN_0x2,
	RD_BIT_0x3_0 => RD_BIT_0x3_0,
	WRITE_EN_PIN_0x3 => WRITE_EN_PIN_0x3,
	RD_BIT_0x4_0 => RD_BIT_0x4_0,
	WRITE_EN_PIN_0x4 => WRITE_EN_PIN_0x4,
	RD_BIT_0x5_0 => RD_BIT_0x5_0,
	WRITE_EN_PIN_0x5 => WRITE_EN_PIN_0x5,
	RD_BIT_0x6_0 => RD_BIT_0x6_0,
	WRITE_EN_PIN_0x6 => WRITE_EN_PIN_0x6,
	RD_BIT_0x7_0 => RD_BIT_0x7_0,
	WRITE_EN_PIN_0x7 => WRITE_EN_PIN_0x7,
	RD_BIT_0x8_0 => RD_BIT_0x8_0,
	RD_BIT_0x9_1 => RD_BIT_0x9_1,
	RD_BIT_0xa_2 => RD_BIT_0xa_2,
	RD_BIT_0xb_3 => RD_BIT_0xb_3,
	RD_BIT_0xc_4 => RD_BIT_0xc_4,
	RD_BIT_0xd_5 => RD_BIT_0xd_5,
	RD_BIT_0xe_6 => RD_BIT_0xe_6,
	RD_BIT_0xf_7 => RD_BIT_0xf_7,
	RD_BIT_0x10_0 => RD_BIT_0x10_0,
	WRITE_EN_PIN_0x10 => WRITE_EN_PIN_0x10,
	RD_BIT_0x11_0 => RD_BIT_0x11_0,
	WRITE_EN_PIN_0x11 => WRITE_EN_PIN_0x11,
	RD_BIT_0x12_0 => RD_BIT_0x12_0,
	WRITE_EN_PIN_0x12 => WRITE_EN_PIN_0x12,
	RD_BIT_0x13_0 => RD_BIT_0x13_0,
	RD_BIT_0x14_0 => RD_BIT_0x14_0,
	RD_BIT_0x14_1 => RD_BIT_0x14_1,
	RD_BIT_0x14_2 => RD_BIT_0x14_2,
	RD_BIT_0x15_0 => RD_BIT_0x15_0,
	WRITE_EN_PIN_0x15 => WRITE_EN_PIN_0x15
);

U2:
 EDATA_REG_RISC_WriteRead port map(		
	FAN_SPEED0 => FAN_SPEED0_S_S_S,
	FAN_SPEED1 => FAN_SPEED1_S_S_S,
	FAN_SPEED2 => FAN_SPEED2_S_S_S,
	FAN_SPEED3 => FAN_SPEED3_S_S_S,
	FAN_SPEED4 => FAN_SPEED4_S_S_S,
	FAN_SPEED5 => FAN_SPEED5_S_S_S,
	FAN_SPEED6 => FAN_SPEED6_S_S_S,
	FAN_SPEED7 => FAN_SPEED7_S_S_S,
	SPI_CLK => SPI_CLK_S_S_S,
	SPI_CE => SPI_CE_S_S_S,
	SPI_DO => SPI_DO_S_S_S,
	POWER_CTL => POWER_CTL_S_S_S,
	CK_MP => CK_MP,
	RESET_L => RESET_L,
	WR_DATA => WR_DATA,
	WRITE_EN_PIN_0x0 => WRITE_EN_PIN_0x0,
	RD_BIT_0x0_0 => RD_BIT_0x0_0,
	WRITE_EN_PIN_0x1 => WRITE_EN_PIN_0x1,
	RD_BIT_0x1_0 => RD_BIT_0x1_0,
	WRITE_EN_PIN_0x2 => WRITE_EN_PIN_0x2,
	RD_BIT_0x2_0 => RD_BIT_0x2_0,
	WRITE_EN_PIN_0x3 => WRITE_EN_PIN_0x3,
	RD_BIT_0x3_0 => RD_BIT_0x3_0,
	WRITE_EN_PIN_0x4 => WRITE_EN_PIN_0x4,
	RD_BIT_0x4_0 => RD_BIT_0x4_0,
	WRITE_EN_PIN_0x5 => WRITE_EN_PIN_0x5,
	RD_BIT_0x5_0 => RD_BIT_0x5_0,
	WRITE_EN_PIN_0x6 => WRITE_EN_PIN_0x6,
	RD_BIT_0x6_0 => RD_BIT_0x6_0,
	WRITE_EN_PIN_0x7 => WRITE_EN_PIN_0x7,
	RD_BIT_0x7_0 => RD_BIT_0x7_0,
	WRITE_EN_PIN_0x10 => WRITE_EN_PIN_0x10,
	RD_BIT_0x10_0 => RD_BIT_0x10_0,
	WRITE_EN_PIN_0x11 => WRITE_EN_PIN_0x11,
	RD_BIT_0x11_0 => RD_BIT_0x11_0,
	WRITE_EN_PIN_0x12 => WRITE_EN_PIN_0x12,
	RD_BIT_0x12_0 => RD_BIT_0x12_0,
	WRITE_EN_PIN_0x15 => WRITE_EN_PIN_0x15,
	RD_BIT_0x15_0 => RD_BIT_0x15_0
);

U3:
 EDATA_REG_RISC_ReadOnly port map(		
	SPEED_MONITOR_0 => SPEED_MONITOR_0_S_S_S,
	SPEED_MONITOR_1 => SPEED_MONITOR_1_S_S_S,
	SPEED_MONITOR_2 => SPEED_MONITOR_2_S_S_S,
	SPEED_MONITOR_3 => SPEED_MONITOR_3_S_S_S,
	SPEED_MONITOR_4 => SPEED_MONITOR_4_S_S_S,
	SPEED_MONITOR_5 => SPEED_MONITOR_5_S_S_S,
	SPEED_MONITOR_6 => SPEED_MONITOR_6_S_S_S,
	SPEED_MONITOR_7 => SPEED_MONITOR_7_S_S_S,
	SPI_DI => SPI_DI_S_S_S,
	MODE => MODE,
	RD_BIT_0x8_0 => RD_BIT_0x8_0,
	RD_BIT_0x9_1 => RD_BIT_0x9_1,
	RD_BIT_0xa_2 => RD_BIT_0xa_2,
	RD_BIT_0xb_3 => RD_BIT_0xb_3,
	RD_BIT_0xc_4 => RD_BIT_0xc_4,
	RD_BIT_0xd_5 => RD_BIT_0xd_5,
	RD_BIT_0xe_6 => RD_BIT_0xe_6,
	RD_BIT_0xf_7 => RD_BIT_0xf_7,
	RD_BIT_0x13_0 => RD_BIT_0x13_0,
	RD_BIT_0x14_0 => RD_BIT_0x14_0,
	RD_BIT_0x14_1 => RD_BIT_0x14_1,
	RD_BIT_0x14_2 => RD_BIT_0x14_2
);



end schematics;