📄 edata_reg_risc.vhd
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LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;entity EDATA_REG_RISC isport ( RESET_L : in std_logic; RESET_FRAME_L : in std_logic; CK_MP : in std_logic; RH_WL : in std_logic; EXEC : in std_logic; OP_DONE : out std_logic; ADDRESS : in std_logic_vector(7 downto 0); WR_DATA : in std_logic_vector(7 downto 0); RD_DATA : out std_logic_vector(7 downto 0); FAN_SPEED0 : out std_logic; FAN_SPEED1 : out std_logic; FAN_SPEED2 : out std_logic; FAN_SPEED3 : out std_logic; FAN_SPEED4 : out std_logic; FAN_SPEED5 : out std_logic; FAN_SPEED6 : out std_logic; FAN_SPEED7 : out std_logic; SPI_CLK : out std_logic; SPI_CE : out std_logic; SPI_DO : out std_logic; POWER_CTL : out std_logic; SPEED_MONITOR_0 : in std_logic; SPEED_MONITOR_1 : in std_logic; SPEED_MONITOR_2 : in std_logic; SPEED_MONITOR_3 : in std_logic; SPEED_MONITOR_4 : in std_logic; SPEED_MONITOR_5 : in std_logic; SPEED_MONITOR_6 : in std_logic; SPEED_MONITOR_7 : in std_logic; SPI_DI : in std_logic; MODE : in std_logic_vector(2 downto 0));end EDATA_REG_RISC;architecture schematics of EDATA_REG_RISC iscomponent EDATA_REG_RISC_SelectUnit port ( RESET_L : in std_logic; RESET_FRAME_L : in std_logic; CK_MP : in std_logic; RH_WL : in std_logic; EXEC : in std_logic; OP_DONE : out std_logic; ADDRESS : in std_logic_vector(7 downto 0); WR_DATA : in std_logic_vector(7 downto 0); RD_DATA : out std_logic_vector(7 downto 0); RD_BIT_0x0_0 : in std_logic; WRITE_EN_PIN_0x0 : out std_logic; RD_BIT_0x1_0 : in std_logic; WRITE_EN_PIN_0x1 : out std_logic; RD_BIT_0x2_0 : in std_logic; WRITE_EN_PIN_0x2 : out std_logic; RD_BIT_0x3_0 : in std_logic; WRITE_EN_PIN_0x3 : out std_logic; RD_BIT_0x4_0 : in std_logic; WRITE_EN_PIN_0x4 : out std_logic; RD_BIT_0x5_0 : in std_logic; WRITE_EN_PIN_0x5 : out std_logic; RD_BIT_0x6_0 : in std_logic; WRITE_EN_PIN_0x6 : out std_logic; RD_BIT_0x7_0 : in std_logic; WRITE_EN_PIN_0x7 : out std_logic; RD_BIT_0x8_0 : in std_logic; RD_BIT_0x9_1 : in std_logic; RD_BIT_0xa_2 : in std_logic; RD_BIT_0xb_3 : in std_logic; RD_BIT_0xc_4 : in std_logic; RD_BIT_0xd_5 : in std_logic; RD_BIT_0xe_6 : in std_logic; RD_BIT_0xf_7 : in std_logic; RD_BIT_0x10_0 : in std_logic; WRITE_EN_PIN_0x10 : out std_logic; RD_BIT_0x11_0 : in std_logic; WRITE_EN_PIN_0x11 : out std_logic; RD_BIT_0x12_0 : in std_logic; WRITE_EN_PIN_0x12 : out std_logic; RD_BIT_0x13_0 : in std_logic; RD_BIT_0x14_0 : in std_logic; RD_BIT_0x14_1 : in std_logic; RD_BIT_0x14_2 : in std_logic; RD_BIT_0x15_0 : in std_logic; WRITE_EN_PIN_0x15 : out std_logic);end component;component EDATA_REG_RISC_WriteRead port ( FAN_SPEED0 : out std_logic_vector(0 downto 0); FAN_SPEED1 : out std_logic_vector(0 downto 0); FAN_SPEED2 : out std_logic_vector(0 downto 0); FAN_SPEED3 : out std_logic_vector(0 downto 0); FAN_SPEED4 : out std_logic_vector(0 downto 0); FAN_SPEED5 : out std_logic_vector(0 downto 0); FAN_SPEED6 : out std_logic_vector(0 downto 0); FAN_SPEED7 : out std_logic_vector(0 downto 0); SPI_CLK : out std_logic_vector(0 downto 0); SPI_CE : out std_logic_vector(0 downto 0); SPI_DO : out std_logic_vector(0 downto 0); POWER_CTL : out std_logic_vector(0 downto 0); CK_MP : in std_logic; RESET_L : in std_logic; WR_DATA : in std_logic_vector(7 downto 0); WRITE_EN_PIN_0x0 : in std_logic; RD_BIT_0x0_0 : out std_logic; WRITE_EN_PIN_0x1 : in std_logic; RD_BIT_0x1_0 : out std_logic; WRITE_EN_PIN_0x2 : in std_logic; RD_BIT_0x2_0 : out std_logic; WRITE_EN_PIN_0x3 : in std_logic; RD_BIT_0x3_0 : out std_logic; WRITE_EN_PIN_0x4 : in std_logic; RD_BIT_0x4_0 : out std_logic; WRITE_EN_PIN_0x5 : in std_logic; RD_BIT_0x5_0 : out std_logic; WRITE_EN_PIN_0x6 : in std_logic; RD_BIT_0x6_0 : out std_logic; WRITE_EN_PIN_0x7 : in std_logic; RD_BIT_0x7_0 : out std_logic; WRITE_EN_PIN_0x10 : in std_logic; RD_BIT_0x10_0 : out std_logic; WRITE_EN_PIN_0x11 : in std_logic; RD_BIT_0x11_0 : out std_logic; WRITE_EN_PIN_0x12 : in std_logic; RD_BIT_0x12_0 : out std_logic; WRITE_EN_PIN_0x15 : in std_logic; RD_BIT_0x15_0 : out std_logic);end component;component EDATA_REG_RISC_ReadOnly port ( SPEED_MONITOR_0 : in std_logic_vector(0 downto 0); SPEED_MONITOR_1 : in std_logic_vector(0 downto 0); SPEED_MONITOR_2 : in std_logic_vector(0 downto 0); SPEED_MONITOR_3 : in std_logic_vector(0 downto 0); SPEED_MONITOR_4 : in std_logic_vector(0 downto 0); SPEED_MONITOR_5 : in std_logic_vector(0 downto 0); SPEED_MONITOR_6 : in std_logic_vector(0 downto 0); SPEED_MONITOR_7 : in std_logic_vector(0 downto 0); SPI_DI : in std_logic_vector(0 downto 0); MODE : in std_logic_vector(2 downto 0); RD_BIT_0x8_0 : out std_logic; RD_BIT_0x9_1 : out std_logic; RD_BIT_0xa_2 : out std_logic; RD_BIT_0xb_3 : out std_logic; RD_BIT_0xc_4 : out std_logic; RD_BIT_0xd_5 : out std_logic; RD_BIT_0xe_6 : out std_logic; RD_BIT_0xf_7 : out std_logic; RD_BIT_0x13_0 : out std_logic; RD_BIT_0x14_0 : out std_logic; RD_BIT_0x14_1 : out std_logic; RD_BIT_0x14_2 : out std_logic);end component;signal RD_BIT_0x0_0 : std_logic;signal WRITE_EN_PIN_0x0 : std_logic;signal RD_BIT_0x1_0 : std_logic;signal WRITE_EN_PIN_0x1 : std_logic;signal RD_BIT_0x2_0 : std_logic;signal WRITE_EN_PIN_0x2 : std_logic;signal RD_BIT_0x3_0 : std_logic;signal WRITE_EN_PIN_0x3 : std_logic;signal RD_BIT_0x4_0 : std_logic;signal WRITE_EN_PIN_0x4 : std_logic;signal RD_BIT_0x5_0 : std_logic;signal WRITE_EN_PIN_0x5 : std_logic;signal RD_BIT_0x6_0 : std_logic;signal WRITE_EN_PIN_0x6 : std_logic;signal RD_BIT_0x7_0 : std_logic;signal WRITE_EN_PIN_0x7 : std_logic;signal RD_BIT_0x8_0 : std_logic;signal RD_BIT_0x9_1 : std_logic;signal RD_BIT_0xa_2 : std_logic;⌨️ 快捷键说明
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