📄 lpc17xx.h
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__IO uint32_t DT; /*!< Offset: 0x03C (R/W) Dead time Register */
__IO uint32_t CP; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */
__IO uint32_t CAP0; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */
__IO uint32_t CAP1; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */
__IO uint32_t CAP2; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */
__I uint32_t INTEN; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */
__O uint32_t INTEN_SET; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */
__O uint32_t INTEN_CLR; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */
__I uint32_t CNTCON; /*!< Offset: 0x05C (R/ ) Count Control read address Register */
__O uint32_t CNTCON_SET; /*!< Offset: 0x060 ( /W) Count Control set address Register */
__O uint32_t CNTCON_CLR; /*!< Offset: 0x064 ( /W) Count Control clear address Register */
__I uint32_t INTF; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */
__O uint32_t INTF_SET; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */
__O uint32_t INTF_CLR; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */
__O uint32_t CAP_CLR; /*!< Offset: 0x074 ( /W) Capture clear address Register */
} LPC_MCPWM_TypeDef;
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
/** @brief Quadrature Encoder Interface (QEI) register structure definition */
typedef struct
{
__O uint32_t CON; /*!< Offset: 0x000 ( /W) Control Register */
__I uint32_t STAT; /*!< Offset: 0x004 (R/ ) Encoder Status Register */
__IO uint32_t CONF; /*!< Offset: 0x008 (R/W) Configuration Register */
__I uint32_t POS; /*!< Offset: 0x00C (R/ ) Position Register */
__IO uint32_t MAXPOS; /*!< Offset: 0x010 (R/W) Maximum position Register */
__IO uint32_t CMPOS0; /*!< Offset: 0x014 (R/W) Position compare Register 0 */
__IO uint32_t CMPOS1; /*!< Offset: 0x018 (R/W) Position compare Register 1 */
__IO uint32_t CMPOS2; /*!< Offset: 0x01C (R/W) Position compare Register 2 */
__I uint32_t INXCNT; /*!< Offset: 0x020 (R/ ) Index count Register */
__IO uint32_t INXCMP0; /*!< Offset: 0x024 (R/W) Index compare Register 0 */
__IO uint32_t LOAD; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */
__I uint32_t TIME; /*!< Offset: 0x02C (R/ ) Velocity timer Register */
__I uint32_t VEL; /*!< Offset: 0x030 (R/ ) Velocity counter Register */
__I uint32_t CAP; /*!< Offset: 0x034 (R/ ) Velocity capture Register */
__IO uint32_t VELCOMP; /*!< Offset: 0x038 (R/W) Velocity compare Register */
__IO uint32_t FILTER;
uint32_t RESERVED0[998];
__O uint32_t IEC; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */
__O uint32_t IES; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */
__I uint32_t INTSTAT; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */
__I uint32_t IE; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */
__O uint32_t CLR; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */
__O uint32_t SET; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */
} LPC_QEI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
typedef struct
{
__IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */
} LPC_CANAF_RAM_TypeDef;
/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
typedef struct /* Acceptance Filter Registers */
{
__IO uint32_t AFMR; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */
__IO uint32_t SFF_sa; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */
__IO uint32_t SFF_GRP_sa; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */
__IO uint32_t EFF_sa; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */
__IO uint32_t EFF_GRP_sa; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */
__IO uint32_t ENDofTable; /*!< Offset: 0x014 (R/W) End of AF Tables Register */
__I uint32_t LUTerrAd; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */
__I uint32_t LUTerr; /*!< Offset: 0x01C (R/ ) LUT Error Register */
__IO uint32_t FCANIE; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */
__IO uint32_t FCANIC0; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */
__IO uint32_t FCANIC1; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */
} LPC_CANAF_TypeDef;
/** @brief Controller Area Network Central (CANCR) register structure definition */
typedef struct /* Central Registers */
{
__I uint32_t TxSR; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */
__I uint32_t RxSR; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */
__I uint32_t MSR; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */
} LPC_CANCR_TypeDef;
/** @brief Controller Area Network Controller (CAN) register structure definition */
typedef struct /* Controller Registers */
{
__IO uint32_t MOD; /*!< Offset: 0x000 (R/W) CAN Mode Register */
__O uint32_t CMR; /*!< Offset: 0x004 ( /W) CAN Command Register */
__IO uint32_t GSR; /*!< Offset: 0x008 (R/W) CAN Global Status Register */
__I uint32_t ICR; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */
__IO uint32_t IER; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */
__IO uint32_t BTR; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */
__IO uint32_t EWL; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */
__I uint32_t SR; /*!< Offset: 0x01C (R/ ) CAN Status Register */
__IO uint32_t RFS; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */
__IO uint32_t RID; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */
__IO uint32_t RDA; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */
__IO uint32_t RDB; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */
__IO uint32_t TFI1; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */
__IO uint32_t TID1; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */
__IO uint32_t TDA1; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */
__IO uint32_t TDB1; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */
__IO uint32_t TFI2; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */
__IO uint32_t TID2; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */
__IO uint32_t TDA2; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */
__IO uint32_t TDB2; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */
__IO uint32_t TFI3; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */
__IO uint32_t TID3; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */
__IO uint32_t TDA3; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */
__IO uint32_t TDB3; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */
} LPC_CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
typedef struct /* Common Registers */
{
__I uint32_t IntStat; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */
__I uint32_t IntTCStat; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */
__O uint32_t IntTCClear; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */
__I uint32_t IntErrStat; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */
__O uint32_t IntErrClr; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */
__I uint32_t RawIntTCStat; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */
__I uint32_t RawIntErrStat; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */
__I uint32_t EnbldChns; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */
__IO uint32_t SoftBReq; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */
__IO uint32_t SoftSReq; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */
__IO uint32_t SoftLBReq; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */
__IO uint32_t SoftLSReq; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */
__IO uint32_t Config; /*!< Offset: 0x030 (R/W) DMA Configuration Register */
__IO uint32_t Sync; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */
} LPC_GPDMA_TypeDef;
/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
typedef struct /* Channel Registers */
{
__IO uint32_t CSrcAddr; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */
__IO uint32_t CDestAddr; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */
__IO uint32_t CLLI; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */
__IO uint32_t CControl; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */
__IO uint32_t CConfig; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */
} LPC_GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
/** @brief Universal Serial Bus (USB) register structure definition */
typedef struct
{
__I uint32_t Revision; /*!< Offset: 0x000 (R/ ) Revision Register */
__IO uint32_t Control; /*!< Offset: 0x004 (R/W) Control Register */
__IO uint32_t CommandStatus; /*!< Offset: 0x008 (R/W) Command / Status Register */
__IO uint32_t InterruptStatus; /*!< Offset: 0x00C (R/W) Interrupt Status Register */
__IO uint32_t InterruptEnable; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */
__IO uint32_t InterruptDisable; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */
__IO uint32_t HCCA; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */
__I uint32_t PeriodCurrentED; /*!< Offset: 0x01C (R/ ) Register */
__IO uint32_t ControlHeadED; /*!< Offset: 0x020 (R/W) Register */
__IO uint32_t ControlCurrentED; /*!< Offset: 0x024 (R/W) Register */
__IO uint32_t BulkHeadED; /*!< Offset: 0x028 (R/W) Register */
__IO uint32_t BulkCurrentED; /*!< Offset: 0x02C (R/W) Register */
__I uint32_t DoneHead; /*!< Offset: 0x030 (R/ ) Register */
__IO uint32_t FmInterval; /*!< Offset: 0x034 (R/W) Register */
__I uint32_t FmRemaining; /*!< Offset: 0x038 (R/ ) Register */
__I uint32_t FmNumber; /*!< Offset: 0x03C (R/ ) Register */
__IO uint32_t PeriodicStart; /*!< Offset: 0x040 (R/W) Register */
__IO uint32_t LSTreshold; /*!< Offset: 0x044 (R/W) Register */
__IO uint32_t RhDescriptorA; /*!< Offset: 0x048 (R/W) Register */
__IO uint32_t RhDescriptorB; /*!< Offset: 0x04C (R/W) Register */
__IO uint32_t RhStatus; /*!< Offset: 0x050 (R/W) Register */
__IO uint32_t RhPortStatus1; /*!< Offset: 0x054 (R/W) Register */
__IO uint32_t RhPortStatus2; /*!< Offset: 0x05C (R/W) Register */
uint32_t RESERVED0[40];
__I uint32_t Module_ID; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */
/* USB On-The-Go Registers */
__I uint32_t IntSt; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */
__IO uint32_t IntEn; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */
__O uint32_t IntSet; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */
__O uint32_t IntClr; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */
__IO uint32_t StCtrl; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */
__IO uint32_t Tmr; /*!< Offset: 0x114 (R/W) OTG Timer Register */
uint32_t RESERVED1[58];
/* USB Device Interrupt Registers */
__I uint32_t DevIntSt; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */
__IO uint32_t DevIntEn; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */
__O uint32_t DevIntClr; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */
__O uint32_t DevIntSet; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */
/* USB Device SIE Command Registers */
__O uint32_t CmdCode; /*!< Offset: 0x210 (R/W) USB Command Code Register */
__I uint32_t CmdData; /*!< Offset: 0x214 (R/W) USB Command Data Register */
/* USB Device Transfer Registers */
__I uint32_t RxData; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */
__O uint32_t TxData; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */
__I uint32_t RxPLen; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */
__O uint32_t TxPLen; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */
__IO uint32_t Ctrl; /*!< Offset: 0x228 (R/W) USB Control Register */
__O uint32_t DevIntPri; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */
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