📄 lpc17xx.h
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__O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
};
__IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
__IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
__I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
__I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
__IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
__IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
uint32_t RESERVED0;
__IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
uint32_t RESERVED1;
__IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
uint32_t RESERVED2[6];
__IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
__IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
__IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
} LPC_UART1_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
/** @brief Serial Peripheral Interface (SPI) register structure definition */
typedef struct
{
__IO uint32_t SPCR; /*!< Offset: 0x000 SPI Control Register (R/W) */
__I uint32_t SPSR; /*!< Offset: 0x004 SPI Status Register (R/) */
__IO uint32_t SPDR; /*!< Offset: 0x008 SPI Data Register (R/W) */
__IO uint32_t SPCCR; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */
uint32_t RESERVED0[3];
__IO uint32_t SPINT; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */
} LPC_SPI_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
/** @brief Synchronous Serial Communication (SSP) register structure definition */
typedef struct
{
__IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */
__IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */
__IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */
__I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */
__IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */
__IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */
__IO uint32_t RIS; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */
__IO uint32_t MIS; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */
__IO uint32_t DMACR; /*!< Offset: 0x024 (R/W) DMA Control Register */
} LPC_SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
/** @brief Inter-Integrated Circuit (I2C) register structure definition */
typedef struct
{
__IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */
__I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */
__IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */
__IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */
__IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */
__IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */
__O uint32_t CONCLR; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */
__IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */
__IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */
__IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */
__IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */
__I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */
__IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */
__IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */
__IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */
__IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */
} LPC_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
/** @brief Inter IC Sound (I2S) register structure definition */
typedef struct
{
__IO uint32_t DAO; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */
__IO uint32_t DAI; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */
__O uint32_t TXFIFO; /*!< Offset: 0x008 ( /W) Transmit FIFO */
__I uint32_t RXFIFO; /*!< Offset: 0x00C (R/ ) Receive FIFO */
__I uint32_t STATE; /*!< Offset: 0x010 (R/W) Status Feedback Register */
__IO uint32_t DMA1; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */
__IO uint32_t DMA2; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */
__IO uint32_t IRQ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */
__IO uint32_t TXRATE; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */
__IO uint32_t RXRATE; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */
__IO uint32_t TXBITRATE; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */
__IO uint32_t RXBITRATE; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */
__IO uint32_t TXMODE; /*!< Offset: 0x030 (R/W) Transmit mode control Register */
__IO uint32_t RXMODE; /*!< Offset: 0x034 (R/W) Receive mode control Register */
} LPC_I2S_TypeDef;
/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
/** @brief Repetitive Interrupt Timer (RIT) register structure definition */
typedef struct
{
__IO uint32_t RICOMPVAL;
__IO uint32_t RIMASK;
__IO uint32_t RICTRL;
__IO uint32_t RICOUNTER;
} LPC_RIT_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
/** @brief Real-Time Clock (RTC) register structure definition */
typedef struct
{
__IO uint32_t ILR; /*!< Offset: 0x000 (R/W) Interrupt Location Register */
uint32_t RESERVED0;
__IO uint32_t CCR; /*!< Offset: 0x008 (R/W) Clock Control Register */
__IO uint32_t CIIR; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */
__IO uint32_t AMR; /*!< Offset: 0x010 (R/W) Alarm Mask Register */
__I uint32_t CTIME0; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */
__I uint32_t CTIME1; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */
__I uint32_t CTIME2; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */
__IO uint32_t SEC; /*!< Offset: 0x020 (R/W) Seconds Counter Register */
__IO uint32_t MIN; /*!< Offset: 0x024 (R/W) Minutes Register */
__IO uint32_t HOUR; /*!< Offset: 0x028 (R/W) Hours Register */
__IO uint32_t DOM; /*!< Offset: 0x02C (R/W) Day of Month Register */
__IO uint32_t DOW; /*!< Offset: 0x030 (R/W) Day of Week Register */
__IO uint32_t DOY; /*!< Offset: 0x034 (R/W) Day of Year Register */
__IO uint32_t MONTH; /*!< Offset: 0x038 (R/W) Months Register */
__IO uint32_t YEAR; /*!< Offset: 0x03C (R/W) Years Register */
__IO uint32_t CALIBRATION; /*!< Offset: 0x040 (R/W) Calibration Value Register */
__IO uint32_t GPREG0; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */
__IO uint32_t GPREG1; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */
__IO uint32_t GPREG2; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */
__IO uint32_t GPREG3; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */
__IO uint32_t GPREG4; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */
__IO uint32_t RTC_AUXEN; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */
__IO uint32_t RTC_AUX; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */
__IO uint32_t ALSEC; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */
__IO uint32_t ALMIN; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */
__IO uint32_t ALHOUR; /*!< Offset: 0x068 (R/W) Alarm value for Hours */
__IO uint32_t ALDOM; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */
__IO uint32_t ALDOW; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */
__IO uint32_t ALDOY; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */
__IO uint32_t ALMON; /*!< Offset: 0x078 (R/W) Alarm value for Months */
__IO uint32_t ALYEAR; /*!< Offset: 0x07C (R/W) Alarm value for Year */
} LPC_RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
/** @brief Watchdog Timer (WDT) register structure definition */
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */
__IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */
__O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */
__I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */
__IO uint32_t WDCLKSEL;
} LPC_WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
/** @brief Analog-to-Digital Converter (ADC) register structure definition */
typedef struct
{
__IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */
__IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */
uint32_t RESERVED0;
__IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */
__I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */
__I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */
__IO uint32_t ADTRM; /*!< Offset: 0x034 (R/W) ADC trim Register */
} LPC_ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
/** @brief Digital-to-Analog Converter (DAC) register structure definition */
typedef struct
{
__IO uint32_t CR; /*!< Offset: 0x000 (R/W) D/A Converter Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) DAC Control register */
__IO uint32_t CNTVAL; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */
} LPC_DAC_TypeDef;
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
typedef struct
{
__I uint32_t CON; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */
__O uint32_t CON_SET; /*!< Offset: 0x004 ( /W) PWM Control set address Register */
__O uint32_t CON_CLR; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */
__I uint32_t CAPCON; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */
__O uint32_t CAPCON_SET; /*!< Offset: 0x010 ( /W) Capture Control set address Register */
__O uint32_t CAPCON_CLR; /*!< Offset: 0x014 ( /W) Event Control clear address Register */
__IO uint32_t TC0; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */
__IO uint32_t TC1; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */
__IO uint32_t TC2; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */
__IO uint32_t LIM0; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */
__IO uint32_t LIM1; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */
__IO uint32_t LIM2; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */
__IO uint32_t MAT0; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */
__IO uint32_t MAT1; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */
__IO uint32_t MAT2; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */
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