📄 lpc17xx.h
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/******************************************************************************
* @file: LPC17xx.h
* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC17xx Device Series
* @version: V1.10
* @date: 24. September 2010
*----------------------------------------------------------------------------
*
* @note
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __LPC17xx_H__
#define __LPC17xx_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
/** @addtogroup LPC17xx_System
* @{
*/
/** @brief IRQ interrupt source definition */
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** LPC17xx Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */
I2C1_IRQn = 11, /*!< I2C1 Interrupt */
I2C2_IRQn = 12, /*!< I2C2 Interrupt */
SPI_IRQn = 13, /*!< SPI Interrupt */
SSP0_IRQn = 14, /*!< SSP0 Interrupt */
SSP1_IRQn = 15, /*!< SSP1 Interrupt */
PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ADC_IRQn = 22, /*!< A/D Converter Interrupt */
BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
USB_IRQn = 24, /*!< USB Interrupt */
CAN_IRQn = 25, /*!< CAN Interrupt */
DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
I2S_IRQn = 27, /*!< I2S Interrupt */
ENET_IRQn = 28, /*!< Ethernet Interrupt */
RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */
CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "system_LPC17xx.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control (SC) ------------------------------------------*/
/** @brief System Control (SC) register structure definition */
typedef struct
{
__IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
uint32_t RESERVED0[31];
__IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
__IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
__I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
__O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
uint32_t RESERVED1[4];
__IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
__IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
__I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
__O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
uint32_t RESERVED2[4];
__IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
__IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
uint32_t RESERVED3[15];
__IO uint32_t CCLKCFG; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */
__IO uint32_t USBCLKCFG; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */
__IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
__IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
__IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
uint32_t RESERVED4[10];
__IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
uint32_t RESERVED5[1];
__IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
__IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
uint32_t RESERVED6[12];
__IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
uint32_t RESERVED7[7];
__IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
__IO uint32_t IRCTRIM; /* Clock Dividers */
__IO uint32_t PCLKSEL0; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */
__IO uint32_t PCLKSEL1; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */
uint32_t RESERVED8[4];
__IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
__IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
__IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
} LPC_SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
/** @brief Pin Connect Block (PINCON) register structure definition */
typedef struct
{
__IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */
__IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */
__IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */
__IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */
__IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */
__IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */
__IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */
__IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */
__IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */
__IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */
__IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */
uint32_t RESERVED0[5];
__IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */
__IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */
__IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */
__IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */
__IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */
__IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */
__IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */
__IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */
__IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */
__IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */
__IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */
__IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */
__IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */
__IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */
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