📄 lh79520_uart_driver.c
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RCPC->periphclkctrl = RCPC->periphclkctrl | (0x1 << 1);
}
else if ((UART_REGS_T *) uartcfgptr->regptr == UART2)
{
/* UART2 selected */
/* Disable UART pins on muxed lines for UART0 */
IOCON->ssimux &= ~(SSIMUX_UT2RXD | SSIMUX_UT2TXD);
/* Disable the selected UART clock in the RCPC. */
RCPC->periphclkctrl = RCPC->periphclkctrl | (0x1 << 2);
}
status = _NO_ERROR;
uartcfgptr->init = FALSE;
}
return status;
}
/***********************************************************************
*
* Function: uart_ioctl
*
* Purpose: UART configuration block
*
* Processing:
* This function is a large case block. Based on the passed function
* and option values, set or get the appropriate UART parameter.
*
* Parameters:
* devid: Pointer to UART config structure
* cmd: ioctl command
* arg: ioctl argument
*
* Outputs: None
*
* Returns: The status of the ioctl operation
*
* Notes: None
*
**********************************************************************/
STATUS uart_ioctl(INT_32 devid,
INT_32 cmd,
INT_32 arg)
{
UNS_32 tmp;
UART_REGS_T *uartregs;
UART_CFG_T *uartcfgptr = (UART_CFG_T *) devid;
STATUS status = _ERROR;
if (uartcfgptr->init == TRUE)
{
status = _NO_ERROR;
uartregs = uartcfgptr->regptr;
switch (cmd)
{
case UART_ENABLE:
/* Enable or disable the UART */
if ((INT_32) arg == 1)
{
/* Enable UART */
uartregs->cr |= UARTCR_ENABLE;
}
else
{
/* Disable UART */
uartregs->cr &= ~UARTCR_ENABLE;
}
break;
case UART_TX_ENABLE:
/* Enable or disable the UART transmit */
if ((INT_32) arg == 1)
{
/* Enable UART transmit */
uartregs->cr |= UARTCR_TXE;
}
else
{
/* Disable UART transmit */
uartregs->cr &= ~UARTCR_TXE;
}
break;
case UART_RX_ENABLE:
/* Enable or disable the UART receive */
if ((INT_32) arg == 1)
{
/* Enable UART receive */
uartregs->cr |= UARTCR_RXE;
}
else
{
/* Disable UART receive */
uartregs->cr &= ~UARTCR_RXE;
}
break;
case SIR_ENABLE:
/* Enable or disable the SIR */
if ((INT_32) arg == 1)
{
/* Enable SIR */
uartregs->cr |= UARTCR_SIREN;
}
else
{
/* Disable SIR */
uartregs->cr &= ~UARTCR_SIREN;
}
break;
case UART_SET_BAUD_RATE:
/* Set the bps rate */
switch (arg)
{
case BPS_2400:
uartregs->ibrd = UARTBRINT_2400;
uartregs->fbrd = UARTBRFRAC_2400;
break;
case BPS_4800:
uartregs->ibrd = UARTBRINT_4800;
uartregs->fbrd = UARTBRFRAC_4800;
break;
case BPS_9600:
uartregs->ibrd = UARTBRINT_9600;
uartregs->fbrd = UARTBRFRAC_9600;
break;
case BPS_19200:
uartregs->ibrd = UARTBRINT_19200;
uartregs->fbrd = UARTBRFRAC_19200;
break;
case BPS_38400:
uartregs->ibrd = UARTBRINT_38400;
uartregs->fbrd = UARTBRFRAC_38400;
break;
case BPS_57600:
uartregs->ibrd = UARTBRINT_57600;
uartregs->fbrd = UARTBRFRAC_57600;
break;
case BPS_115200:
uartregs->ibrd = UARTBRINT_115200;
uartregs->fbrd = UARTBRFRAC_115200;
break;
case BPS_230400:
uartregs->ibrd = UARTBRINT_230400;
uartregs->fbrd = UARTBRFRAC_230400;
break;
case BPS_460800:
uartregs->ibrd = UARTBRINT_460800;
uartregs->fbrd = UARTBRFRAC_460800;
break;
default:
/* Baud bps rate */
status = _ERROR;
}
break;
case UART_SET_DATA_BITS:
/* Set the data bit width */
if ((arg >= 5) && (arg <= 8))
{
/* clear the bits */
uartregs->lcr_h &= ~(_BIT(5) | _BIT(6));
uartregs->lcr_h |= _SBF(5,arg-5);
}
else
{
/* Baud data width */
status = _ERROR;
}
break;
case UART_SET_PARITY:
/* Set UART parity */
switch (arg)
{
case UART_PARITY_NONE:
/* Disable parity */
uartregs->lcr_h &= ~UARTLCR_PEN;
break;
case UART_PARITY_ODD:
/* Odd parity */
uartregs->lcr_h |= UARTLCR_PEN;
uartregs->lcr_h &= ~UARTLCR_EPS;
break;
case UART_PARITY_EVEN:
/* Even parity */
uartregs->lcr_h |= UARTLCR_PEN;
uartregs->lcr_h &= ~UARTLCR_EPS;
break;
default:
/* Baud parity */
status = _ERROR;
}
break;
case UART_SET_STOP_BITS:
/* Set the number of stop bits */
if (arg == 1)
{
/* 1 stop bit */
uartregs->lcr_h &= ~UARTLCR_STP2;
}
else if (arg == 2)
{
/* 2 stop bits */
uartregs->lcr_h |= UARTLCR_STP2;
}
else
{
/* Baud data width */
status = _ERROR;
}
break;
case UART_ENABLE_FIFO:
/* Enable or disable the FIFOs */
if ((INT_32) arg == 1)
{
/* Enable FIFOs */
uartregs->lcr_h |= UARTLCR_FEN;
}
else
{
/* Disable FIFOs */
uartregs->lcr_h &= ~UARTLCR_FEN;
}
break;
case UART_ASSERT_BREAK:
/* Assert or de-assert a break */
if (arg == 1)
{
/* Assert break */
uartregs->lcr_h |= UARTLCR_BRK;
}
else
{
/* De-assert break */
uartregs->lcr_h &= ~UARTLCR_BRK;
}
break;
case UART_SET_LOOPBACK:
/* Enable or disable loopback mode */
if (arg == 1)
{
/* Enable loopback mode */
uartregs->cr |= UARTCR_LBE;
}
else
{
/* Disable loopback mode */
uartregs->cr &= ~UARTCR_LBE;
}
break;
case SIR_SET_LOWPOWER:
/* Enables or disables SIR low power mode */
if (arg == 1)
{
/* Enable SIR low power mode */
uartregs->cr |= UARTCR_SIRLP;
}
else
{
/* Disable SIR low power mode */
uartregs->cr &= ~UARTCR_SIRLP;
}
break;
case UART_ENABLE_INTS:
/* Enable selected interrupts */
tmp = ((UNS_32) arg | uartregs->imsc) &
(UARTINT_RX | UARTINT_TX | UARTINT_RT |
UARTINT_FE | UARTINT_PE | UARTINT_BE | UARTINT_OE);
uartregs->imsc = tmp;
break;
case UART_DISABLE_INTS:
/* Disable selected interrupts */
tmp = (UNS_32) arg &
(UARTINT_RX | UARTINT_TX | UARTINT_RT |
UARTINT_FE | UARTINT_PE | UARTINT_BE | UARTINT_OE);
uartregs->imsc &= ~tmp;
break;
case UART_GET_STATUS:
/* Return a UART status */
switch (arg)
{
case UART_GET_ENABLE:
/* Return UART enabled status */
if ((uartregs->cr & UARTCR_ENABLE) != 0)
{
/* UART is enabled */
status = 1;
}
else
{
/* UART is disabled */
status = 0;
}
break;
case UART_GET_TX_ENABLE:
/* Return UART transmit enabled status */
if ((uartregs->cr & UARTCR_TXE) != 0)
{
/* UART transmit is enabled */
status = 1;
}
else
{
/* UART transmit is disabled */
status = 0;
}
break;
case UART_GET_RX_ENABLE:
/* Return UART receive enabled status */
if ((uartregs->cr & UARTCR_RXE) != 0)
{
/* UART receive is enabled */
status = 1;
}
else
{
/* UART receive is disabled */
status = 0;
}
break;
case SIR_GET_ENABLE:
/* Return UART SIR enabled status */
if ((uartregs->cr & UARTCR_SIREN) != 0)
{
/* UART SIR is enabled */
status = 1;
}
else
{
/* UART SIR is disabled */
status = 0;
}
break;
case UART_GET_BAUD_RATE:
/* Return the baud rate enumeration */
switch (uartregs->ibrd)
{
case UARTBRINT_2400:
status = BPS_2400;
break;
case UARTBRINT_4800:
status = BPS_4800;
break;
case UARTBRINT_9600:
status = BPS_9600;
break;
case UARTBRINT_19200:
status = BPS_19200;
break;
case UARTBRINT_38400:
status = BPS_38400;
break;
case UARTBRINT_57600:
status = BPS_57600;
break;
case UARTBRINT_115200:
status = BPS_115200;
break;
case UARTBRINT_230400:
status = BPS_230400;
break;
case UARTBRINT_460800:
status = BPS_460800;
break;
default:
/* Unknown bps rate */
status = _ERROR;
break;
}
break;
case UART_GET_DATA_BITS:
/* Return the number of data bits (5 to 8) */
switch (uartregs->lcr_h & UARTLCR_WLEN8)
{
case UARTLCR_WLEN5:
status = 5;
break;
case UARTLCR_WLEN6:
status = 6;
break;
case UARTLCR_WLEN7:
status = 7;
break;
case UARTLCR_WLEN8:
default:
status = 8;
break;
}
break;
case UART_GET_PARITY:
/* Return selected parity */
if ((uartregs->lcr_h & UARTLCR_PEN) != 0)
{
/* Parity is enabled */
if ((uartregs->lcr_h & UARTLCR_EPS) != 0)
{
/* Even parity */
status = UART_PARITY_EVEN;
}
else
{
/* Odd parity */
status = UART_PARITY_ODD;
}
}
else
{
/* No parity */
status = UART_PARITY_NONE;
}
break;
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