lh79520_rcpc_driver.h

Sharp Lh79520 RTC 驱动源码.

/***********************************************************************
 * $Workfile:   lh79520_rcpc_driver.h  $
 * $Revision:   1.0  $
 * $Author:   LiJ  $
 * $Date:   Jul 07 2003 16:41:00  $
 *
 * Project: LH79520 RCPC driver
 *
 * Description:
 *     This file contains driver support for the RCPC module on the
 *     LH79520
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh79520/include/lh79520_rcpc_driver.h-arc  $
 * 
 *    Rev 1.0   Jul 07 2003 16:41:00   LiJ
 * Initial revision.
 * 
 *
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/

#ifndef LH79520_RCPC_DRIVER_H
#define LH79520_RCPC_DRIVER_H

#ifdef __cplusplus
extern "C" {
#endif

#include "lh79520_rcpc.h"

/***********************************************************************
 * RCPC device configuration commands (IOCTL commands and arguments)
 **********************************************************************/

/* RCPC device commands (IOCTL commands) */
typedef enum {
    RCPC_WRITE_LOCK,    /* Lock the RCPC from writing, no args */
    RCPC_WRITE_UNLOCK,  /* Unlock the RCPC, write possible, no arg */
    RCPC_SET_HCLK_CLK_SRC,  /* Set HCLK clock source, arg = 1, clock from
                            CLKIN pin. arg = 0 clock from oscillator */
    RCPC_ENABLE_MAIN_CRYSTAL,   /* Valid only HCLK source is from CLKIN pin
                            Enable the main oscillator is running even HCLK
                            driven from CLKIN pin */
    RCPC_SET_CLKOUT_CLK_SRC,    /* Select CLKOUT pin clock source. arg 
                            defined in RCPC_CLKOUT_SRC_T */
                    
    RCPC_POWER_DOWN_MODE,   /* Set power down mode, arg defined in 
                            RCPC_POWER_DOWN_T */
    RCPC_SOFT_RESET,    /* Issue a software reset to the chip. arg = 0 reset
                            chip and RTC, arg = 1 reset chip only */            
    RCPC_REMAP_MEM,     /* Remap the memory using REMAP bit in RCPC. arg 
                            defined in RCPC_REMAP_T */          
    RCPC_CLEAR_RESET,   /* Clear the reset status register. arg defined in
                            RCPC_RESET_SRC_T */
    RCPC_SET_CPU_DIV,   /* Set the CPU clock divider, arg = divider  */
    RCPC_SET_HCLK_DIV,  /* Set the HCLK clock divider, arg = divider */
    RCPC_SET_PWM0_DIV,  /* Set the PWM0 clock divider, arg = divider */
    RCPC_SET_PWM1_DIV,  /* Set the PWM1 clock divider, arg = divider */
    RCPC_SET_LCD_DIV,   /* Set the LCD clock divider, arg = divider */
    RCPC_SET_SSP_DIV,   /* Set the SSP clock divider, arg = divider */
    RCPC_ENABLE_IP_CLOCK,   /* Enable the clock from RCPC to Peripherals.
                            arg defined in RCPC_IP_CLK_T */
    RCPC_DISABLE_IP_CLOCK,  /* Disable the clock from RCPC to Peripherals 
                            arg defined in RCPC_IP_CLK_T*/
    RCPC_SET_RTC_CLK_SRC,   /* Set the clock source for RTC. arg = 1, 
                            select 32Khz clock source, arg = 0, select
                            1Hz clock source */
    RCPC_SET_UART0_CLK_SRC, /* Set the clock source for UART0. arg = 1
                            select external clock source, arg = 0, select
                            internal clock */
    RCPC_SET_UART1_CLK_SRC, /* Set the clock source for UART1. arg = 1
                            select external clock source, arg = 0, select
                            internal clock */
    RCPC_SET_UART2_CLK_SRC, /* Set the clock source for UART2. arg = 1
                            select external clock source, arg = 0, select
                            internal clock */
    RCPC_SET_LCD_CLK_SRC,   /* Set the clock source for LCD. arg = 1
                            select external LCDCLK clock source, arg = 0, select
                            internal HCLK clock */
    RCPC_GET_STATUS         /* Get RCPC status, use an argument type of
                            RCPC_IOCTL_STS_T as the argument to return the
                            correct status */
} RCPC_IOCTL_CMD_T;
                
                
/* RCPC device arguments for RCPC_GET_STATUS command (IOCTL arguments) */
typedef enum {
    RCPC_GET_RESET_SOURCE,  /* Get the cause for reset. Returns 
                            RESET_FROM_EXTERNAL, RESET_FROM_WDT or _ERROR */
    RCPC_GET_CPU_CLK,       /* Get the CPU clock. Return CPU clock in Hz */
    RCPC_GET_HCLK_CLK,      /* Get the HCLK clock. Return HCLK clock in Hz */
    RCPC_GET_LCD_CLK,       /* Get the LCD clock. Return LCD clock in Hz */
    RCPC_GET_PWM0_CLK,      /* Get the PWM0 clock. Return PWM0 clock in Hz */
    RCPC_GET_PWM1_CLK,      /* Get the PWM1 clock. Return PWM1 clock in Hz */
    RCPC_GET_SSP_CLK        /* Get the SSP clock. Return SSP clock in Hz */
    
} RCPC_IOCTL_STS_T;
                    
/* RCPC device arguments for CLKOUT pin source clock */
typedef enum {
    CLKOUT_MHZ_14P7456,     /* CLKOUT select 14.7 Mhz */
    CLKOUT_MHZ_309P6576,    /* CLKOUT select 309.6 Mhz  */
    CLKOUT_FCLK,            /* CLKOUT select FCLK */
    CLKOUT_HCLK             /* CLKOUT select HCLK   */
} RCPC_CLKOUT_SRC_T;    

typedef enum {
    MCU_ACTIVE_MODE,    /* MCU set in active mode */
    MCU_STANDBY_MODE,   /* MCU set in stand by mode */
    MCU_SLEEP_MODE,     /* MCU set in sleep mode */
    MCU_STOP1_MODE,     /* MCU set in stop 1 mode */
    MCU_STOP2_MODE      /* MCU set in stop 2 mode */
} RCPC_POWER_MODE_T;    

typedef enum {
    REMAP_EXTERNAL_SRAM_ADDR0,  /* REMAP the external SRAM to address 0x0 */
    REMAP_SDRAM_ADDR0,          /* REMAP the external SDRAM to address 0x0 */
    REMAP_INTERNAL_SRAM_ADDR0   /* REMAP the internal SRAM to address 0x0 */
} RCPC_REMAP_T; 

typedef enum {
    RESET_FROM_EXTERNAL,        /* RESET is from external RESET pin */
    RESET_FROM_WDT              /* RESET is from watchdog timer */
} RCPC_RESET_SRC_T; 

typedef enum {
    RCPC_CLK_RTC,       /* clock from RCPC to RTC controller */
    RCPC_CLK_PWM1,      /* clock from RCPC to PWM1 controller */
    RCPC_CLK_PWM0,      /* clock from RCPC to PWM0 controller */
    RCPC_CLK_T23,       /* clock from RCPC to Timer 2 and 3 controller */
    RCPC_CLK_T01,       /* clock from RCPC to Timer 0 and 1 controller */
    RCPC_CLK_U2,        /* clock from RCPC to UART2 controller */
    RCPC_CLK_U1,        /* clock from RCPC to UART1 controller */
    RCPC_CLK_U0,        /* clock from RCPC to UART0 controller */
    RCPC_CLK_SSP,       /* clock from RCPC to SSP controller */
    RCPC_CLK_LCD,       /* clock from RCPC to LCD controller */
    RCPC_CLK_SDC,       /* clock from RCPC to SDRAM controller */
    RCPC_CLK_DMA        /* clock from RCPC to DMA controller */
} RCPC_IP_CLK_T;
    
/***********************************************************************
 * RCPC device configuration structure
 **********************************************************************/

/* RCPC device configuration structure */
typedef struct
{
    INT_32 init;       /* Device initialized flag */
    RCPC_REGS_T *regptr; /* Pointer to RCPC registers */
} RCPC_CFG_T;

/***********************************************************************
 * RCPC driver functions
 **********************************************************************/
/* Open the watchdog timer */
INT_32 rcpc_open(void *ipbase, INT_32 arg);

/* Close the watchdog timer */
STATUS rcpc_close(INT_32 devid);

/* Watchdog timer configuration block */
STATUS rcpc_ioctl(INT_32 devid,
                 INT_32 cmd,
                 INT_32 arg);

/* RCPC read function (stub only) */
INT_32 rcpc_read(INT_32 devid,
                void *buffer,
                INT_32 max_bytes);

/* RCPC write function (stub only) */
INT_32 rcpc_write(INT_32 devid,
                 void *buffer,
                 INT_32 n_bytes);

#ifdef __cplusplus
}
#endif

#endif /* LH79520_RCPC_DRIVER_H */