sysdef.h

Infineon公司有一款实现SHDSL协议（ADSL协议的变种）的芯片

#define  SOCRATES_RBC_E_RME_E   0x80
                                       /* STAT_E register bit settings.      */

#define  SOCRATES_STAT_E_XRESA_E 0x04
#define  SOCRATES_STAT_E_RRESA_E 0x08

#define  SOCRATES_XBC_E_XME_E   0x80
                                       /* CMD_E register bit settings.       */

#define  SOCRATES_CMD_E_XRES_E  0x01
#define  SOCRATES_CMD_E_RRES_E  0x02
                                        /* RSTAT_E register bits */

#define  SOCRATES_RSTAT_E_RAB_E 0x02
#define  SOCRATES_RSTAT_E_FCS_E 0x04
#define  SOCRATES_RSTAT_E_RDO_E 0x08
#define  SOCRATES_RSTAT_E_CSRF_E 0x10

                                       /* ISTATR register bits              */

#define SOCRATES_ISTATR_ATSC     0x80
#define SOCRATES_ISTATR_TST2C    0x10
#define SOCRATES_ISTATR_OVHC     0x08

/* ============================= */              
/* EPIC register                 */
/* settings.                     */
/* ============================= */

#ifdef MUX
                                           /* PCM interface register.             */

    #define EPIC_PMOD    0x20+EPIC_BASE
    #define EPIC_PBNR    0x22+EPIC_BASE
    #define EPIC_POFD    0x24+EPIC_BASE
    #define EPIC_POFU    0x26+EPIC_BASE
    #define EPIC_PCSR    0x28+EPIC_BASE
    #define EPIC_PICM    0x2A+EPIC_BASE  S

                                           /* CFI interface register.             */

    #define EPIC_CMD1       0x2C+EPIC_BASE
    #define EPIC_CMD2       0x2E+EPIC_BASE
    #define EPIC_CBNR       0x30+EPIC_BASE
    #define EPIC_CTAR       0x32+EPIC_BASE
    #define EPIC_CBSR       0x34+EPIC_BASE
    #define EPIC_CSCR       0x36+EPIC_BASE
                                           /* Memory access register.             */

    #define EPIC_MACR       0x00+EPIC_BASE
    #define EPIC_MAAR       0x02+EPIC_BASE
    #define EPIC_MADR       0x04+EPIC_BASE

                                           /* Sync. transfer register.            */

    #define EPIC_STDA       0x06+EPIC_BASE
    #define EPIC_STDB       0x08+EPIC_BASE
    #define EPIC_SARA       0x0A+EPIC_BASE
    #define EPIC_SARB       0x0C+EPIC_BASE
    #define EPIC_SAXA       0x0E+EPIC_BASE
    #define EPIC_SAXB       0x10+EPIC_BASE
    #define EPIC_STCR       0x12+EPIC_BASE 

                                           /* Monitor/Feat. control reg.          */

    #define EPIC_MFAIR      0x14+EPIC_BASE
    #define EPIC_MFFIFO     0x16+EPIC_BASE

                                           /* Status control register.            */

    #define EPIC_CIFIFO     0x18+EPIC_BASE
    #define EPIC_STAR       0x1A+EPIC_BASE
    #define EPIC_CMDR       0x1A+EPIC_BASE
    #define EPIC_ISTA       0x1C+EPIC_BASE
    #define EPIC_MASK       0x1C+EPIC_BASE
    #define EPIC_OMDR       0x1E+EPIC_BASE
    #define EPIC_VNSR       0x3A+EPIC_BASE

#endif
#ifdef DEMUX


                                           /* PCM interface register.             */

    #define EPIC_PMOD       0x00+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_PBNR       0x01+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_POFD       0x02+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_POFU       0x03+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_PCSR       0x04+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_PICM       0x05+EPIC_BASE+EPIC_DEMUX_SWITCH

                                           /* CFI interface register.             */

    #define EPIC_CMD1       0x06+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_CMD2       0x07+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_CBNR       0x08+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_CTAR       0x09+EPIC_BASE+EPIC_DEMUX_SWITCH

    #define EPIC_CBSR       0x0A+EPIC_BASE+EPIC_DEMUX_SWITCH
    #define EPIC_CSCR       0x0B+EPIC_BASE+EPIC_DEMUX_SWITCH

    #define EPIC_DEMUX_SWITCH    0x10

                                           /* Memory access register.             */

    #define EPIC_MACR       0x00+EPIC_BASE
    #define EPIC_MAAR       0x01+EPIC_BASE
    #define EPIC_MADR       0x02+EPIC_BASE

                                           /* Sync. transfer register.            */

    #define EPIC_STDA       0x03+EPIC_BASE
    #define EPIC_STDB       0x04+EPIC_BASE
    #define EPIC_SARA       0x05+EPIC_BASE
    #define EPIC_SARB       0x06+EPIC_BASE
    #define EPIC_SAXA       0x07+EPIC_BASE
    #define EPIC_SAXB       0x08+EPIC_BASE
    #define EPIC_STCR       0x09+EPIC_BASE

                                           /* Monitor/Feat. control reg.          */

    #define EPIC_MFAIR      0x0A+EPIC_BASE
    #define EPIC_MFFIFO     0x0B+EPIC_BASE

                                           /* Status control register.            */

    #define EPIC_CIFIFO     0x0C+EPIC_BASE
    #define EPIC_TIMR       0x0C+EPIC_BASE
    #define EPIC_STAR       0x0D+EPIC_BASE
    #define EPIC_CMDR       0x0D+EPIC_BASE
    #define EPIC_ISTA       0x0E+EPIC_BASE
    #define EPIC_MASK       0x0E+EPIC_BASE
    #define EPIC_OMDR       0x0F+EPIC_BASE

    #ifdef EPIC_ADDR_BUGFIX
        #define EPIC_OMDR_SHIFT 0xF0+EPIC_BASE
    #endif

    #define EPIC_VNSR       0x0D+EPIC_BASE+EPIC_DEMUX_SWITCH

#endif

/* ============================= */
/* FALC register                 */
/* settings.                     */
/* ============================= */

                                       /* Transmit and receive FIFO.          */
#define FALC_XFIFO          0x00+FALC_BASE
#define FALC_RFIFO          FALC_XFIFO

                                       /* Command register.                   */
#define FALC_CMDR           0x02+FALC_BASE

                                       /* Mode register.                      */
#define FALC_MODE           0x03+FALC_BASE

                                       /* Receive address high 1-2.           */
#define FALC_RAH1           0x04+FALC_BASE
#define FALC_RAH2           0x05+FALC_BASE

                                       /* Receive address low 1-2.            */
#define FALC_RAL1           0x06+FALC_BASE
#define FALC_RAL2           0x07+FALC_BASE

                                       /* Interrupt port configuration.       */
#define FALC_IPC            0x08+FALC_BASE

                                       /* Common config register 1+2.         */
#define FALC_CCR1           0x09+FALC_BASE
#define FALC_CCR2           0x0A+FALC_BASE

                                       /* Receive timeslot reg 1-4.           */
#define FALC_RTR1           0x0C+FALC_BASE
#define FALC_RTR2           0x0D+FALC_BASE
#define FALC_RTR3           0x0E+FALC_BASE
#define FALC_RTR4           0x0F+FALC_BASE

                                       /* Transmit timeslot reg 1-4.          */
#define FALC_TTR1           0x10+FALC_BASE
#define FALC_TTR2           0x11+FALC_BASE
#define FALC_TTR3           0x12+FALC_BASE
#define FALC_TTR4           0x13+FALC_BASE

                                       /* Interrupt mask reg 0-4.             */
#define FALC_IMR0           0x14+FALC_BASE
#define FALC_IMR1           0x15+FALC_BASE
#define FALC_IMR2           0x16+FALC_BASE
#define FALC_IMR3           0x17+FALC_BASE
#define FALC_IMR4           0x18+FALC_BASE

                                       /* Frame mode reg 0-2.                */
#define FALC_FMR0           0x1C+FALC_BASE
#define FALC_FMR1           0x1D+FALC_BASE
#define FALC_FMR2           0x1E+FALC_BASE
 
                                       /* Channel loop back.                 */
#define FALC_LOOP           0x1F+FALC_BASE

                                       /* Transmit service word.             */
#define FALC_XSW            0x20+FALC_BASE

                                       /* Transmit spare bits.               */
#define FALC_XSP            0x21+FALC_BASE

                                       /* Transmit control 0-1.              */
#define FALC_XC0            0x22+FALC_BASE
#define FALC_XC1            0x23+FALC_BASE

                                       /* Receive control 0-1.               */
#define FALC_RC0            0x24+FALC_BASE
#define FALC_RC1            0x25+FALC_BASE

                                       /* Transmit puls mask 0-2.            */
#define FALC_XPM0           0x26+FALC_BASE
#define FALC_XPM1           0x27+FALC_BASE
#define FALC_XPM2           0x28+FALC_BASE

                                       /* Transp. service word mask.         */
#define FALC_TSWM           0x29+FALC_BASE

                                       /* Idle channel code.                 */
#define FALC_IDLE           0x2B+FALC_BASE

                                       /* Transmit SA4-8 bit register.       */
#define FALC_XSA4           0x2C+FALC_BASE
#define FALC_XSA5           0x2D+FALC_BASE
#define FALC_XSA6           0x2E+FALC_BASE
#define FALC_XSA7           0x2F+FALC_BASE
#define FALC_XSA8           0x30+FALC_BASE

                                       /* Framer mode reg.                   */
#define FALC_FMR3           0x31+FALC_BASE

                                       /* Idle channel register 1-4.         */
#define FALC_ICB1           0x32+FALC_BASE
#define FALC_ICB2           0x33+FALC_BASE
#define FALC_ICB3           0x34+FALC_BASE
#define FALC_ICB4           0x35+FALC_BASE

                                       /* Line interface mode 0-1.           */
#define FALC_LIM0           0x36+FALC_BASE
#define FALC_LIM1           0x37+FALC_BASE

                                       /* Pulse count detection.              */
#define FALC_PCD            0x38+FALC_BASE

                                       /* Pulse count recovery.               */
#define FALC_PCR            0x39+FALC_BASE

                                       /* Line interface mode 2.             */
#define FALC_LIM2           0x3A+FALC_BASE

                                       /* Loop code register 1-3.            */
#define FALC_LCR1           0x3B+FALC_BASE
#define FALC_LCR2           0x3C+FALC_BASE
#define FALC_LCR3           0x3D+FALC_BASE

                                       /* System interf. control 1-3.        */
#define FALC_SIC1           0x3E+FALC_BASE
#define FALC_SIC2           0x3F+FALC_BASE
#define FALC_SIC3           0x40+FALC_BASE
                                          
                                       /* Clock mode register 1-2.           */
#define FALC_CMR1           0x44+FALC_BASE
#define FALC_CMR2           0x45+FALC_BASE

                                       /* Global configuration register.     */
#define FALC_GCR            0x46+FALC_BASE

                                       /* Error 2nd mask register.           */
#define FALC_ESM            0x47+FALC_BASE

                                       /* Disable error counter.             */
#define FALC_DEC            0x60+FALC_BASE

                                       /* Trans. and rec. CAS1-16 reg.       */
#define FALC_XS1            0x70+FALC_BASE
#define FALC_RS1            FALC_XS1
#define FALC_XS2            0x71+FALC_BASE
#define FALC_RS2            FALC_XS2
#define FALC_XS3            0x72+FALC_BASE
#define FALC_RS3            FALC_XS3
#define FALC_XS4            0x73+FALC_BASE
#define FALC_RS4            FALC_XS4
#define FALC_XS5            0x74+FALC_BASE
#define FALC_RS5            FALC_XS5
#define FALC_XS6            0x75+FALC_BASE
#define FALC_RS6            FALC_XS6
#define FALC_XS7            0x76+FALC_BASE
#define FALC_RS7            FALC_XS7
#define FALC_XS8            0x77+FALC_BASE
#define FALC_RS8            FALC_XS8
#define FALC_XS9            0x78+FALC_BASE
#define FALC_RS9            FALC_XS9
#define FALC_XS10           0x79+FALC_BASE
#define FALC_RS10           FALC_XS10
#define FALC_XS11           0x7A+FALC_BASE
#define FALC_RS11           FALC_XS11
#define FALC_XS12           0x7B+FALC_BASE
#define FALC_RS12           FALC_XS12
#define FALC_XS13           0x7C+FALC_BASE
#define FALC_RS13           FALC_XS13
#define FALC_XS14           0x7D+FALC_BASE
#define FALC_RS14           FALC_XS14
#define FALC_XS15           0x7E+FALC_BASE
#define FALC_RS15           FALC_XS15
#define FALC_XS16           0x7F+FALC_BASE
#define FALC_RS16           FALC_XS16

#define FALC_PC1            0x80+FALC_BASE
#define FALC_PC2            0x81+FALC_BASE
#define FALC_PC3            0x82+FALC_BASE
#define FALC_PC4            0x83+FALC_BASE
#define FALC_PC5            0x84+FALC_BASE
#define FALC_GPC1           0x85+FALC_BASE
#define FALC_PC6            0x86+FALC_BASE
#define FALC_CMDR2          0x87+FALC_BASE

#define FALC_GCM1           0x92+FALC_BASE
#define FALC_GCM2           0x93+FALC_BASE
#define FALC_GCM3           0x94+FALC_BASE
#define FALC_GCM4           0x95+FALC_BASE
#define FALC_GCM5           0x96+FALC_BASE
#define FALC_GCM6           0x97+FALC_BASE