📄 sysdef.h
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#define CLLOSWF 0x90
#define CLDFAIL 0x9F
/*Symbolical Constants for the Transceiver Status TSTAT */
#define SDSL_POWER_DOWN 0x00
#define SEND_SINGLE_PULSES 0x01
#define INITIALIZATION 0x02
#define PROCESSING_CL 0x03
#define TR_ANALOG_LOOP_CLOSED 0x04
#define TR_ANALOG_LOOP_ACTIVE 0x05
#define NON_TR_ANALOG_LOOP_CLOSED 0x06
#define NON_TR_ANALOG_LOOP_ACTIVE 0x07
#define GHS_STARTUP 0x10
#define GHS_TRANSACTION_AUTO 0x11
#define LINE_PROBING 0x12
#define GHS_FINISHED 0x13
#define GHS_SILENCE 0x14
#define GHS_STARTUP_FAILED 0x15
#define GHS_TRANSACTION_FAILED 0x16
#define LINE_PROBING_FAILED 0x17
#define GHS_NO_COMMON_MODE 0x18
/* LTU: 0x20 */
#define WAIT_FOR_CR 0x21
#define TRANSMIT_SC 0x22
#define TRANSMIT_TC 0x23
#define TRANSMIT_FC 0x24
/* NTU: 0x28 */
#define TRANSMIT_CR 0x28
#define CRSR_SILENCE 0x29
#define TRANSMIT_SR 0x2A
#define TRANSMIT_TR 0x2B
/* Exception States */
/* LTU: 0x30 */
#define SR_NOT_DET 0x30
#define TR_NOT_DET 0x31
/* NTU: 0x38 */
#define TC_NOT_DET 0x38
#define FC_NOT_DET 0x39
#define DATA_EXCEPTION 0x32
#define DATA 0x40
#define CRC_ANOMALY 0x41
#define LOSW_DEFECT 0x42
#define LOOP_ATTEN_DEF 0x44
#define SNR_MARGIN_DEF 0x48
#define LOSW_FAILURE 0x50
#define SOCRATES_TSTAT_ICMD 0x80
/* ============================= */
/* Timer structures */
/* ============================= */
/* structure to hold state and timestamp for interval measurement between
transceiver states */
typedef struct
{
WORD8 State; /* transceiver state */
WORD8 Time_High; /* high byte of time counter */
WORD8 Time_Low; /* low byte of time counter */
} T_TIMER_ENTRY;
/* this global structure carries all the data necessary for
measurement of time intervals between transceiver states */
typedef struct
{
WORD8 Status; /* carries the actual status of the
timer as IDLE, ACTIVE, RUNNING
or FINISHED */
WORD8 Mode; /* can be TIMER_MODE_NORMAL,
TIMER_MODE_ALL_STATES or
TIMER_MODE_FORCE_INDICATION */
WORD8 Index; /* gives the number of latest entry made */
WORD8 Stop_State; /* Transceiver state to stop measurement */
WORD16 Time_Counter; /* timeunits elapsed since start state */
WORD8 Length; /* number of entries made */
WORD8 Start_State; /* transceiver state to start measurement */
T_TIMER_ENTRY Entry[0xFF]; /* entry with state and timestamp */
} T_TIMER;
#define TIMER_MODE_NORMAL 0x00
#define TIMER_MODE_ALL_STATES 0x01
#define TIMER_MODE_FORCE_INDICATION 0x02
#define TIMER_STATUS_IDLE 0x00
#define TIMER_STATUS_ACTIVE 0x01
#define TIMER_STATUS_RUNNING 0x02
#define TIMER_STATUS_FINISHED 0x03
typedef struct
{
WORD16 Address;
WORD16 Counter; /* the actual time units to wait */
WORD8 Old_Value; /* register value to restore */
WORD8 Last_Value; /* register value last read */
} T_REGISTER_TIMER;
/* ============================= */
/* Interrupt Queue */
/* ============================= */
/* possible interrupt types */
typedef enum
{
NO_INT,
ATSC_INT, /* activation transceiver state change interrupt */
TST2C_INT,
OVHC_INT,
EOC_RX_INT,
EOC_TX_INT,
EOC_ERROR_INT,
HDLC_RX_INT,
HDLC_TX_INT,
HDLC_ERROR_INT,
CL_UP_INT,
SNR_INT,
RESET_RFIFO_E,
INT_REG_TIMER
} T_INT_TYPE;
/* data structure for interrupt information */
typedef struct
{
/* Interrupt type */
T_INT_TYPE Int_Type;
/* Value to indicate */
WORD32 Value;
} T_INT_DATA;
/* Structure to buffer interrupt events */
typedef struct
{
WORD8 Head,
Tail;
T_INT_DATA Data[256];
} T_INT_FIFO;
/* ============================= */
/* EOC transmission */
/* ============================= */
typedef struct
{
WORD8 Rx_Error,
Tx_Error;
/* device status */
WORD8 State;
/* tx current buffer index */
WORD16 Tx_Curr,
/* rx current buffer index */
Rx_Curr;
/* transmit byte counter */
WORD16 Tx_Cnt,
/* receive byte counter */
Rx_Cnt;
/* receive FIFO size */
WORD8 Rx_Bufsize,
/* transmit FIFO size */
Tx_Bufsize;
/* transmit buffer */
WORD8 Tx_Buffer[EOC_RX_BUF_SIZE],
/* receive buffer */
Rx_Buffer[EOC_RX_BUF_SIZE];
} T_EOC;
/* ============================= */
/* Socrates register */
/* ============================= */
/* General register. */
#define SOCRATES_DSEL 0x00+SOCRATES_BASE
#define SOCRATES_IDENT 0x01+SOCRATES_BASE
#define SOCRATES_CONF 0x02+SOCRATES_BASE
#define SOCRATES_MASK 0x03+SOCRATES_BASE
#define SOCRATES_ISTA 0x04+SOCRATES_BASE
/* Customer interface register. */
#define SOCRATES_CIF_CON_1 0x10+SOCRATES_BASE
#define SOCRATES_CIF_CON_2 0x11+SOCRATES_BASE
#define SOCRATES_CIF_CON_3 0x12+SOCRATES_BASE
#define SOCRATES_TDM_OFF 0x13+SOCRATES_BASE
#define SOCRATES_HDLC_OFF 0x14+SOCRATES_BASE
#define SOCRATES_HDLC_WIN 0x15+SOCRATES_BASE
#define SOCRATES_HDLC_BIT 0x16+SOCRATES_BASE
/* Loop delay register. */
#define SOCRATES_LDEL_LO 0x17+SOCRATES_BASE
#define SOCRATES_LDEL_HI 0x18+SOCRATES_BASE
/* HDLC register for B-cha & Z-bits. */
#define SOCRATES_ISTA_BZ 0x20+SOCRATES_BASE
#define SOCRATES_MASK_BZ 0x21+SOCRATES_BASE
#define SOCRATES_STAT_BZ 0x22+SOCRATES_BASE
#define SOCRATES_CMD_BZ 0x22+SOCRATES_BASE
#define SOCRATES_MODE_BZ 0x23+SOCRATES_BASE
#define SOCRATES_EXM_BZ 0x24+SOCRATES_BASE
#define SOCRATES_SAP1_BZ 0x26+SOCRATES_BASE
#define SOCRATES_SAP2_BZ 0x27+SOCRATES_BASE
#define SOCRATES_RBCL_BZ 0x27+SOCRATES_BASE
#define SOCRATES_RBCH_BZ 0x28+SOCRATES_BASE
#define SOCRATES_TEI1_BZ 0x28+SOCRATES_BASE
#define SOCRATES_TEI2_BZ 0x29+SOCRATES_BASE
#define SOCRATES_RSTA_BZ 0x29+SOCRATES_BASE
#define SOCRATES_TM_BZ 0x2A+SOCRATES_BASE
#define SOCRATES_RFIFO_BZ 0x2B+SOCRATES_BASE
#define SOCRATES_XFIFO_BZ 0x2B+SOCRATES_BASE
/* HDLC register for EOC-cha. */
#define SOCRATES_ISTA_E 0x30+SOCRATES_BASE
#define SOCRATES_MASK_E 0x31+SOCRATES_BASE
#define SOCRATES_STAT_E 0x32+SOCRATES_BASE
#define SOCRATES_CMD_E 0x33+SOCRATES_BASE
#define SOCRATES_MODE_E 0x34+SOCRATES_BASE
#define SOCRATES_SADDR_E 0x35+SOCRATES_BASE
#define SOCRATES_RBC_E 0x36+SOCRATES_BASE
#define SOCRATES_XBC_E 0x36+SOCRATES_BASE
#define SOCRATES_RFIFO_E 0x37+SOCRATES_BASE
#define SOCRATES_XFIFO_E 0x37+SOCRATES_BASE
/* G.hs register. */
#define SOCRATES_SMODE 0x3D+SOCRATES_BASE
#define SOCRATES_TCMD 0x6E+SOCRATES_BASE
#define SOCRATES_TSTAT 0x3E+SOCRATES_BASE
#define SOCRATES_GHRB 0x3F+SOCRATES_BASE
/* Transceiver register. */
#define SOCRATES_ISTATR 0x40+SOCRATES_BASE
#define SOCRATES_MASKTR 0x41+SOCRATES_BASE
#define SOCRATES_TRAN_CON_1 0x42+SOCRATES_BASE
#define SOCRATES_TRAN_CON_2 0x43+SOCRATES_BASE
#define SOCRATES_TRAN_CON_3 0x44+SOCRATES_BASE
#define SOCRATES_TRAN_CON_4 0x45+SOCRATES_BASE
#define SOCRATES_POW_BOFF 0x46+SOCRATES_BASE
#define SOCRATES_RATE_CON_1 0x47+SOCRATES_BASE
#define SOCRATES_RATE_CON_2 0x48+SOCRATES_BASE
#define SOCRATES_TX_SYNCW_1 0x49+SOCRATES_BASE
#define SOCRATES_TX_SYNCW_2 0x4A+SOCRATES_BASE
#define SOCRATES_TX_EOC_1 0x4B+SOCRATES_BASE
#define SOCRATES_TX_EOC_2 0x4C+SOCRATES_BASE
#define SOCRATES_TX_EOC_3 0x4D+SOCRATES_BASE
#define SOCRATES_TX_CRC 0x4E+SOCRATES_BASE
#define SOCRATES_TX_OVERH_1 0x4F+SOCRATES_BASE
#define SOCRATES_TX_OVERH_2 0x50+SOCRATES_BASE
#define SOCRATES_TRSTAT_1 0x51+SOCRATES_BASE
#define SOCRATES_TRSTAT_2 0x52+SOCRATES_BASE
#define SOCRATES_RX_SYNCW_1 0x53+SOCRATES_BASE
#define SOCRATES_RX_SYNCW_2 0x54+SOCRATES_BASE
#define SOCRATES_RX_EOC_1 0x55+SOCRATES_BASE
#define SOCRATES_RX_EOC_2 0x56+SOCRATES_BASE
#define SOCRATES_RX_EOC_3 0x57+SOCRATES_BASE
#define SOCRATES_RX_CRC 0x58+SOCRATES_BASE
#define SOCRATES_RX_OVERH_1 0x59+SOCRATES_BASE
#define SOCRATES_RX_OVERH_2 0x5A+SOCRATES_BASE
#define SOCRATES_LINELOSS 0x5B+SOCRATES_BASE
#define SOCRATES_SIGQUAL 0x5C+SOCRATES_BASE
#define SOCRATES_CLRCNT 0x5D+SOCRATES_BASE
#define SOCRATES_FEBECNT 0x5E+SOCRATES_BASE
#define SOCRATES_NEBECNT 0x5F+SOCRATES_BASE
#define SOCRATES_PEAK_LO 0x60+SOCRATES_BASE
#define SOCRATES_PEAK_HI 0x61+SOCRATES_BASE
#define SOCRATES_CVCNT 0x62+SOCRATES_BASE
#define SOCRATES_ESCNT 0x63+SOCRATES_BASE
#define SOCRATES_SESCNT 0x64+SOCRATES_BASE
#define SOCRATES_LOSWSCNT 0x65+SOCRATES_BASE
#define SOCRATES_UASCNT 0x66+SOCRATES_BASE
#define SOCRATES_BYTE_BOFF 0x6A+SOCRATES_BASE
#define SOCRATES_BIT_BOFF 0x6B+SOCRATES_BASE
#define SOCRATES_TBYTE_BCNT 0x6C+SOCRATES_BASE
/* ============================= */
/* Socrates register bits */
/* ============================= */
/* ISTA register bit settings. */
#define SOCRATES_ISTA_HDLCBZ 0x01
#define SOCRATES_ISTA_HDLCE 0x02
#define SOCRATES_ISTA_TRAN 0x04
/* ISTA_BZ register bit settings. */
#define SOCRATES_ISTA_BZ_XDU 0x04
#define SOCRATES_ISTA_BZ_XPR 0x10
#define SOCRATES_ISTA_BZ_RFO 0x20
#define SOCRATES_ISTA_BZ_RPF 0x40
#define SOCRATES_ISTA_BZ_RME 0x80
/* STAT_BZ register bit settings. */
#define SOCRATES_STAT_BZ_XFW 0x40
#define SOCRATES_STAT_BZ_XDOV 0x80
/* CMD_BZ register bit settings. */
#define SOCRATES_CMD_BZ_XRES 0x01
#define SOCRATES_CMD_BZ_XME 0x02
#define SOCRATES_CMD_BZ_XTF 0x08
#define SOCRATES_CMD_BZ_RRES 0x40
#define SOCRATES_CMD_BZ_RMC 0x80
/* ISTA_E register bit settings. */
#define SOCRATES_ISTA_E_XDU_E 0x01
#define SOCRATES_ISTA_E_XPR_E 0x02
#define SOCRATES_ISTA_E_XDOV_E 0x04
#define SOCRATES_ISTA_E_RFO_E 0x08
#define SOCRATES_ISTA_E_RPF_E 0x10
#define SOCRATES_ISTA_E_GHDBR 0x20
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