sysdef.h

Infineon公司有一款实现SHDSL协议（ADSL协议的变种）的芯片

#define MUX_TFSC_CLEAR  REG_MUX_SOC &=  ~0x02
#define MUX_RCLK_SET    REG_MUX_SOC |=  0x04
#define MUX_RCLK_CLEAR  REG_MUX_SOC &=  ~0x04
#define MUX_REG0_SET    REG_MUX_SOC |=  0x08
#define MUX_REG0_CLEAR  REG_MUX_SOC &=  ~0x08
#define MUX_REG1_SET    REG_MUX_SOC |=  0x10
#define MUX_REG1_CLEAR  REG_MUX_SOC &=  ~0x10
#define MUX_REG2_SET    REG_MUX_SOC |=  0x20
#define MUX_REG2_CLEAR  REG_MUX_SOC &=  ~0x20
#define MUX_RFSC0_SET   REG_MUX_SOC |=  0x40
#define MUX_RFSC0_CLEAR REG_MUX_SOC &=  ~0x40
#define MUX_RFSC1_SET   REG_MUX_SOC |=  0x80
#define MUX_RFSC1_CLEAR REG_MUX_SOC &=  ~0x80
#define MUX_CLK0_SET    REG_MUX_CLK |=  0x01
#define MUX_CLK0_CLEAR  REG_MUX_CLK &=  ~0x01
#define MUX_CLK1_SET    REG_MUX_CLK |=  0x02
#define MUX_CLK1_CLEAR  REG_MUX_CLK &=  ~0x02
#define MUX_CLK2_SET    REG_MUX_CLK |=  0x04
#define MUX_CLK2_CLEAR  REG_MUX_CLK &=  ~0x04
#define MUX_FSC0_SET    REG_MUX_CLK |=  0x10
#define MUX_FSC0_CLEAR  REG_MUX_CLK &=  ~0x10
#define MUX_FSC1_SET    REG_MUX_CLK |=  0x20
#define MUX_FSC1_CLEAR  REG_MUX_CLK &=  ~0x20
#define MUX_FSC2_SET    REG_MUX_CLK |=  0x40
#define MUX_FSC2_CLEAR  REG_MUX_CLK &=  ~0x40

#define DIV0_SET        REG_DIV0 |=  0x01
#define DIV0_CLEAR      REG_DIV0 &=  ~0x01
#define DIV1_SET        REG_DIV0 |=  0x02
#define DIV1_CLEAR      REG_DIV0 &=  ~0x02
#define DIV2_SET        REG_DIV0 |=  0x04
#define DIV2_CLEAR      REG_DIV0 &=  ~0x04
#define DIV3_SET        REG_DIV0 |=  0x08
#define DIV3_CLEAR      REG_DIV0 &=  ~0x08
#define DIV4_SET        REG_DIV0 |=  0x10
#define DIV4_CLEAR      REG_DIV0 &=  ~0x10
#define DIV5_SET        REG_DIV0 |=  0x20
#define DIV5_CLEAR      REG_DIV0 &=  ~0x20
#define DIV6_SET        REG_DIV0 |=  0x40
#define DIV6_CLEAR      REG_DIV0 &=  ~0x40
#define DIV7_SET        REG_DIV0 |=  0x80
#define DIV7_CLEAR      REG_DIV0 &=  ~0x80
#define DIV8_SET        REG_DIV1 |=  0x01
#define DIV8_CLEAR      REG_DIV1 &=  ~0x01
#define DIV9_SET        REG_DIV1 |=  0x02
#define DIV9_CLEAR      REG_DIV1 &=  ~0x02

#define MASTER_SET      REG_CTRL |=  0x01
#define MASTER_CLEAR    REG_CTRL &=  ~0x01
#define FL_PGM_SET      REG_CTRL |=  0x02
#define FL_PGM_CLEAR    REG_CTRL &=  ~0x02
#define IM_SET          REG_CTRL |=  0x04
#define IM_CLEAR        REG_CTRL &=  ~0x04
#define OE_SOC_SET      REG_CTRL |=  0x08
#define OE_SOC_CLEAR    REG_CTRL &=  ~0x08
#define S_ALE_SET       REG_CTRL |=  0x10
#define S_ALE_CLEAR     REG_CTRL &=  ~0x10
#define F_TST_SET       REG_CTRL |=  0x40
#define F_TST_CLEAR     REG_CTRL &=  ~0x40

#define S_RST_SET       REG_RESET |=  0x01
#define S_RST_CLEAR     REG_RESET &=  ~0x01
#define F_RST_SET       REG_RESET |=  0x02
#define F_RST_CLEAR     REG_RESET &=  ~0x02
#define E_RST_SET       REG_RESET |=  0x04
#define E_RST_CLEAR     REG_RESET &=  ~0x04

#define COT_LED_ON      REG_LED   |=  0x01
#define COT_LED_OFF     REG_LED   &=  ~0x01


/* ============================= */
/* SMART 2000 register           */
/* settings.                     */
/* ============================= */

                                       /* Mainboard CGR register              */
#define EXT_BOARD_CGR       XVAR(WORD8,0xFF00)
   
                                       /* Mainboard CMR register              */
#define EXT_BOARD_CMR       XVAR(WORD8,0xFF01)  

                                       /* Mainboard Interrupt register        */
#define EXT_BOARD_INT       XVAR(WORD8,0xFB00)  

                                       /* Mainboard MR register               */
#define SMART_2000_MR       XVAR(WORD8,0x300000)         

                                       /* Mainboard LPR register              */
#define SMART_2000_LPR      XVAR(WORD8,0x320000)      

                                       /* Set/clear MR register bits.         */
#define MR_RESST1_SET       SMART_2000_MR |=  0x01    
#define MR_RESST1_CLEAR     SMART_2000_MR &= ~0x01    
#define MR_RESST2_SET       SMART_2000_MR |=  0x02    
#define MR_RESST2_CLEAR     SMART_2000_MR &= ~0x02    
#define MR_DMUXST1_SET      SMART_2000_MR |=  0x04    
#define MR_DMUXST1_CLEAR    SMART_2000_MR &= ~0x04    
#define MR_DMUXST2_SET      SMART_2000_MR |=  0x08    
#define MR_DMUXST2_CLEAR    SMART_2000_MR &= ~0x08    
          
/* ============================= */
/* Defines for download          */
/* ============================= */

                                       /* Start addresses of flash      
                                          buffer of FPGA device.              */
#define FLASH_BUFFER_START  (AOM_BASE+0x8000)    

                                       /* Size of bootloader blocks.          */
#define BLOCK_SIZE_SOC_CODE 0x40
                                       /* Size of FIFO behind FIFO_E */
#define FIFO_SIZE           0x80

/* ============================= */
/* Global definition of all      */
/* G_Eeprom indices.             */
/* ============================= */

                                       /* Define all board configuration indices 
                                          (keep always LAST_CONFIG_INDEX as last
                                          element here).                      */
typedef enum  
{ 
   FIRST_CONFIG_INDEX = 0,
   CONFIG_AUTO        = FIRST_CONFIG_INDEX,
   CONFIG_INTF, 
   CONFIG_MODE,   
   CONFIG_P_CLK, 
   CONFIG_REF_CLK, 
   CONFIG_UC_MODE, 
   CONFIG_FRAME,
   CONFIG_SYNC1,
   CONFIG_SYNC2, 
   LAST_CONFIG_INDEX 
} CONFIG_PARM;

                                       /* Define all debug indices 
                                          (keep always LAST_DEBUG_INDEX as last
                                          element here).                      */
typedef enum  
{ 
   FIRST_DEBUG_INDEX  = LAST_CONFIG_INDEX,
   DEBUG_V24_INT      = FIRST_DEBUG_INDEX,
   DEBUG_V24_TRACE, 
   LAST_DEBUG_INDEX 
} DEBUG_PARM;

                                       /* Define all G.hs configuration indices 
                                          (keep always LAST_GHS_INDEX as last
                                          element here).                      */
typedef enum  
{ 
   FIRST_GHS_INDEX = LAST_DEBUG_INDEX,
   GHS_MODE        = FIRST_GHS_INDEX, 
   GHS_TRAIN,    
   GHS_RES,    
   GHS_PWB,    
   GHS_BURDUR,    
   GHS_TRAN_ID,    
   GHS_NR_B1,    
   GHS_NR_B2,    
   GHS_NR_B3,    
   GHS_NR_B4,    
   GHS_NR_B5,    
   GHS_NR_B6,    
   GHS_NR_B7,    
   GHS_NR_Z1,    
   GHS_NR_Z2,    
   GHS_SCRA,    
   GHS_STUFF,    
   GHS_SYNC1,    
   GHS_SYNC2,    
   LAST_GHS_INDEX,
   LAST_EEPROM_INDEX = LAST_GHS_INDEX 
} GHS_PARM;

/* ============================= */
/* Capability List               */
/* ============================= */

    /* Enum defining the order of parameters in capability list.
        Refer also to standard ITU G.994.1. */
typedef enum
{ 
    CL_REVNR_CL = 0,
    CL_NUMOCT,
    CL_CMD_TYPE,

    CL_REVNR,
    CL_COUNTRY1,
    CL_COUNTRY2,
    CL_PROVIDER1,
    CL_PROVIDER2,
    CL_PROVIDER3,
    CL_PROVIDER4,
    CL_VENDOR1,
    CL_VENDOR2,

    CL_ID_NPAR1,
    CL_ID_SPAR1,

    CL_UP_MAX_NDR,
    CL_UP_MIN_NDR,
    CL_UP_AVG_NDR,
    CL_DN_MAX_NDR,
    CL_DN_MIN_NDR,
    CL_DN_AVG_NDR,

    CL_UP_MAX_LAT,
    CL_UP_AVG_LAT,
    CL_DN_MAX_LAT,
    CL_DN_AVG_LAT,

    CL_SI_NPAR1,
    CL_SI_SPAR1_1,
    CL_ST_SPAR1_2,

    CL_SI_NPAR2,
    CL_SI_SPAR2_1,
    CL_SI_SPAR2_2,

    CL_T_PBODN,
    CL_T_BRATEDN1,
    CL_T_BRATEDN2,
    CL_T_BRATEDN3,
    CL_T_BRATEDN4,
    CL_T_BRATEDN5,
    CL_T_BRATEDN6,
    CL_T_BRATEDN7,
    CL_T_SRATEDN1,
    CL_T_SRATEDN2,

    CL_T_PBOUP,
    CL_T_BRATEUP1,
    CL_T_BRATEUP2,
    CL_T_BRATEUP3,
    CL_T_BRATEUP4,
    CL_T_BRATEUP5,
    CL_T_BRATEUP6,
    CL_T_BRATEUP7,
    CL_T_SRATEUP1,
    CL_T_SRATEUP2,

    CL_PBODN,
    CL_BRATEDN1,
    CL_BRATEDN2,
    CL_BRATEDN3,
    CL_BRATEDN4,
    CL_BRATEDN5,
    CL_BRATEDN6,
    CL_BRATEDN7,
    CL_FIX1_DN,
    CL_FIX2_DN,
    CL_DURATDN,
    CL_SCRAMBDN,

    CL_PBOUP,
    CL_BRATEUP1,
    CL_BRATEUP2,
    CL_BRATEUP3,
    CL_BRATEUP4,
    CL_BRATEUP5,
    CL_BRATEUP6,
    CL_BRATEUP7,
    CL_FIX1_UP,
    CL_FIX2_UP,
    CL_DURATUP,
    CL_SCRAMBUP,

    CL_STUFFBIT_DN,
    CL_SYNCOC1_DN,
    CL_SYNCOC2_DN,

    CL_STUFFBIT_UP,
    CL_SYNCOC1_UP,
    CL_SYNCOC2_UP,

    CL_TPSCLOCK_A,
    CL_TPSCHANNEL_A,
    CL_TPSISDN_A,

    CL_DUALTPS1_A,
    CL_DUALTPS2_A,
    CL_DUALTPS3_A,
    CL_DUALTPS4_A,
    CL_DUALTPS5_A,
    CL_DUALTPS6_A,

    CL_TPSCLOCK_B,
    CL_TPSCHANNEL1_B,
    CL_TPSCHANNEL2_B,
    CL_TPSISDN_B,

    CL_DUALTPS1_B,
    CL_DUALTPS2_B,
    CL_DUALTPS3_B,
    CL_DUALTPS4_B,
    CL_DUALTPS5_B,
    CL_DUALTPS6_B,

    CL_NUMBLOCK,
    CL_NSTDBLOCK1,
    CL_NSTDBLOCK2,

    CAPLIST_LENGTH
} CAP_LIST;

#define SNR_LENGTH 0x40

/* ============================= */
/* Transceiver state machine     */
/* ============================= */

    /* Commands */

#define RESTR           0x01            /* Reset TR state machine */
#define STCL            0x02            /* store downloaded Capabilitylist */
#define DOWNLOAD_CL     0x03            /* This is no firmware command but for internal
                                         use to download list and send STCL */
#define ITEST           0x04
#define PREACT          0x10
#define TRAIN           0x20
#define MTRAIN          0x21
#define PU              0x40
#define PD              0x41
#define CLCRCA          0x81
#define CLLOSWD         0x82
#define CLLAD           0x84
#define CLSNRD          0x88