📄 sysdef.h
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/*******************************************************************************
Copyright (c) 2000, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
*******************************************************************************
Module: SYSDEF
Product ID: 22622.1.0.1
Description: Contains global typedefs and defines.
******************************************************************************/
/* compiler option */
#pragma SB DB CD LA HL(near 0) M167 WL(3)
// Group= SYSDEF
#define PRODUCT "22622.1.0.1"
#ifdef INTEROP
#ifdef DEBUG
#define VERSION "0.15.19.2 IOP debug"
#else
#define VERSION "0.15.19.2 IOP"
#endif
#else
#ifdef DEBUG
#define VERSION "0.15.19.2 debug"
#else
#define VERSION "0.15.19.2"
#endif
#endif /* This define fixes the following
bug of the board: A7..A4 of uC are
connected toA3..A0 of EPIC. */
#define EPIC_ADDR_BUGFIX
/* ============================= */
/* Global typedefs */
/* ============================= */
/* bit */
typedef bit BIT;
/* unsigned char */
typedef unsigned char WORD8;
/* unsigned short int */
typedef unsigned short int WORD16;
/* unsigned long */
typedef unsigned long WORD32;
/* FALSE, TRUE */
typedef enum {FALSE, TRUE} BOOL;
/* ============================= */
/* Interrupt and base-address */
/* settings for ST1. */
/* ============================= */
#ifdef SLOT1
/* Mainboard reset value (MR). */
#define MB_RESET 0xFE
/* Mainboard disable reset value. */
#define MB_RES_Q 0x01
/* Mainboard base address */
#define AOM_BASE 0x00240000
#endif
/* ============================= */
/* Interrupt and base-address */
/* settings for ST2. */
/* ============================= */
#ifdef SLOT2
/* Mainboard reset value (MR). */
#define MB_RESET 0xFD
/* Mainboard disable reset value. */
#define MB_RES_Q 0x02
/* AOM base address */
#define AOM_BASE 0x00250000
#endif
/* ============================= */
/* General base-address */
/* settings. */
/* ============================= */
/* Base address of Socrates. */
#define SOCRATES_BASE 0x0000
/* Base address of FALC. */
#define FALC_BASE 0x0100
/* Base address of EPIC. */
#define EPIC_BASE 0x0200
/* Base address of reg. block 1 */
#define REGBLOCK_BASE 0x0300
/* ============================= */
/* Defines for the interrupt */
/* vector table. */
/* ============================= */
/* Total number of interrupt
sources. */
#define TOTAL_NR_OF_INT 8
#ifdef SLOT1
/* Timer int. source slot1 */
#define INT_TIMER 0
/* SOCRATES int. source slot1 */
#define INT_SOCRATES 2
/* EPIC int. source slot1 */
#define INT_EPIC 4
/* FALC int. source slot1 */
#define INT_FALC 6
#endif
#ifdef SLOT2
/* Timer int. source slot2 */
#define INT_TIMER 1
/* SOCRATES int. source slot2 */
#define INT_SOCRATES 3
/* EPIC int. source slot2 */
#define INT_EPIC 5
/* FALC int. source slot2 */
#define INT_FALC 7
#endif
/* Set level and edged */
#ifdef SLOT1
#define SET_INT0_LEVEL _bfld_(EXICON, 0x0003, 0x0002); CC8IC = 0x68 /* IRL=10, GRL=0 */
#define SET_INT1_LEVEL _bfld_(EXICON, 0x000C, 0x0008); CC9IC = 0x24 /* IRL=09, GRL=0 */
#define SET_INT2_LEVEL _bfld_(EXICON, 0x0030, 0x0020); CC10IC = 0x20 /* IRL=08, GRL=0 */
#endif
#ifdef SLOT2
#define SET_INT0_LEVEL _bfld_(EXICON, 0x00C0, 0x0080); CC11IC = 0x69 /* IRL=10, GRL=1 */
#define SET_INT1_LEVEL _bfld_(EXICON, 0x0300, 0x0200); CC12IC = 0x25 /* IRL=09, GRL=1 */
#define SET_INT2_LEVEL _bfld_(EXICON, 0x0C00, 0x0800); CC13IC = 0x21 /* IRL=08, GRL=1 */
#endif
/* ============================= */
/* Defines for the software */
/* timer table. */
/* ============================= */
#define TIMER_ABORT 0
#define TIMER_WAIT 1
#define TIMER_MEASURE 2
#define TIMER_LED 3
#define TIMER_REG_WAIT 4
/* ============================= */
/* Global macros of */
/* general usage. */
/* ============================= */
/* This macro can be used like
a normal "printf()" call.
Output is only done if global
variable G_V24 is TRUE. The
variable is set in a function
which can receive a message.
Macro must be used with two
brackets: V24_PRINT(("a")). */
#define V24_PRINT(x) if (G_V24 == 0x01) printf x
/* This macro can be used like
a normal "printf()" call.
Output is only done if global
variable G_Eeprom[DEBUG_V24_INT] is TRUE.
It can be global set with the debug_V24
message. This macro is used from
internal function receiving no
messages.
Macro must be used with two
brackets: V24INT_PRINT(("a")). */
#define V24INT_PRINT(x) if (G_Eeprom[DEBUG_V24_INT] == 0x01) printf x
/* This macro can be used like
a normal "while(condition);"
call. If TIMER_ABORT is
expired an automatic timeout
is made. */
#define WHILE_NOT_ABORT(x) G_Abort=FALSE; \
Start_Timer (TIMER_ABORT); \
while ((x) && (!G_Abort)); \
Stop_Timer (TIMER_ABORT)
/* This macro can be used like
a normal "printf()" call.
Macro must be used with two
brackets: TRACE(("a")). */
#define TRACE(x) if (G_Eeprom[DEBUG_V24_TRACE] == 0x01) printf x
/* This macro waits a certain time. The
time can be set in the global timer
array */
#define DELAY() G_Wait=TRUE; \
Start_Timer (TIMER_WAIT); \
while (G_Wait); \
Stop_Timer (TIMER_WAIT)
/* this macro is for selective bit manipulation
in "read and write" (!!!) registers */
#define BFLD(x,y,z) (Out((x),(In(x)&~(y))|(z)))
#ifdef SLOT1
#define SLOT_NR 1
#endif
#ifdef SLOT2
#define SLOT_NR 2
#endif
/* ============================= */
/* Defines for HDLC and EOC */
/* ============================= */
#define EOC_RX_BUF_SIZE 0xFFF
#define HDLC_RX_BUF_SIZE 250
/* ============================= */
/* Defines for configuration */
/* settings. */
/* ============================= */
#define EMUL_MODE 0x02
#define INTF_E1_PCM_SYN 0x00
#define INTF_E1_PCM_PLE 0x01
#define INTF_BIT_SERIAL_0 0x02
#define INTF_BIT_SERIAL_1 0x03
#define INTF_T1 0x04
#define INTF_T1_PCM_SYN 0x05
#define INTF_T1_PCM_PLE 0x06
#define INTF_E1_PCM_PLE_TEST 0x07
#define MODE_COT_EXT 0x00
#define MODE_COT_INT 0x01
#define MODE_RT_LOOP 0x02
#define MODE_RT_FALC 0x03
#define MODE_EXT_PLL 0x04
#define P_CLK_2MHZ 0x00
#define P_CLK_4MHZ 0x01
/* new datasheet 5 */
typedef enum {
REF_CLK_8KHZ,
REF_CLK_2MHZ_1MHZEXT,
REF_CLK_4MHZ_2MHZEXT,
REF_CLK_CIF_4MHZEXT
} T_REF_CLK;
/* old sheet
#define REF_CLK_8KHZ 0*/
/* ============================= */
/* Register block 1 and 2 */
/* settings and macros. */
/* ============================= */
#define REG_OE0 HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0000 )
#define REG_OE1 HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0100 )
#define REG_MUX_SOC HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0200 )
#define REG_MUX_CLK HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0300 )
#define REG_DIV0 HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0400 )
#define REG_DIV1 HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0500 )
#define REG_CTRL HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0600 )
#define REG_RESET HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0700 )
#define REG_LED HVAR(WORD8, AOM_BASE + REGBLOCK_BASE + 0x0800 )
#define OE_PCLK_SET REG_OE0 |= 0x01
#define OE_PCLK_CLEAR REG_OE0 &= ~0x01
#define OE_TFSC_SET REG_OE0 |= 0x02
#define OE_TFSC_CLEAR REG_OE0 &= ~0x02
#define OE_RCLK_SET REG_OE0 |= 0x04
#define OE_RCLK_CLEAR REG_OE0 &= ~0x04
#define OE_RFSC_SET REG_OE0 |= 0x08
#define OE_RFSC_CLEAR REG_OE0 &= ~0x08
#define OE_REFCLK_SET REG_OE0 |= 0x10
#define OE_REFCLK_CLEAR REG_OE0 &= ~0x10
#define OE_SCLK_SET REG_OE1 |= 0x01
#define OE_SCLK_CLEAR REG_OE1 &= ~0x01
#define OE_SYPR_SET REG_OE1 |= 0x02
#define OE_SYPR_CLEAR REG_OE1 &= ~0x02
#define OE_PCLKO_SET REG_OE1 |= 0x04
#define OE_PCLKO_CLEAR REG_OE1 &= ~0x04
#define OE_RCLKO_SET REG_OE1 |= 0x08
#define OE_RCLKO_CLEAR REG_OE1 &= ~0x08
#define OE_REFCLKO_SET REG_OE1 |= 0x10
#define OE_REFCLKO_CLEAR REG_OE1 &= ~0x10
#define OE_DIN_SET REG_OE1 |= 0x20
#define OE_DIN_CLEAR REG_OE1 &= ~0x20
#define MUX_PCLK_SET REG_MUX_SOC |= 0x01
#define MUX_PCLK_CLEAR REG_MUX_SOC &= ~0x01
#define MUX_TFSC_SET REG_MUX_SOC |= 0x02
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