📄 config.c
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}
/* Check training mode */
if (G_Eeprom[CONFIG_FRAME] > 0x03)
{
error = 7;
error_text = "FRAME";
}
/* V24 control message:
When processing. */
if (error == 0)
{
switch (G_Eeprom[CONFIG_AUTO])
{
case 0x00:
//V24_PRINT (("no auto start mode, "));
break;
case 0x01:
V24_PRINT (("auto start mode not longer supported, "));
break;
case 0x02:
V24_PRINT (("emulation mode, "));
break;
}
switch (G_Eeprom[CONFIG_INTF])
{
case 0x00:
V24_PRINT (("E1/PCM synchronous mode, "));
break;
case 0x01:
V24_PRINT (("E1/PCM plesiochronous mode, "));
break;
case 0x02:
V24_PRINT (("bitserial mode Receive Clock Input (RCFDIR=0), "));
break;
case 0x03:
V24_PRINT (("bitserial mode Receive Clock Output (RCFDIR=1), "));
break;
case 0x04:
V24_PRINT (("T1 mode, "));
break;
case 0x05:
V24_PRINT (("T1/PCM synchronous mode, "));
break;
case 0x06:
V24_PRINT (("T1/PCM plesiochronous mode, "));
break;
case 0x07:
V24_PRINT (("E1/PCM plesiochronous Test mode, "));
break;
}
switch (G_Eeprom[CONFIG_MODE])
{
case 0x00:
V24_PRINT (("COT external timed, "));
break;
case 0x01:
V24_PRINT (("COT internal timed, "));
break;
case 0x02:
V24_PRINT (("RT loop timed, "));
break;
case 0x03:
V24_PRINT (("RT FALC PLL, "));
break;
case 0x04:
V24_PRINT (("external PLL, "));
break;
}
switch (G_Eeprom[CONFIG_P_CLK])
{
case 0x00:
V24_PRINT (("PCM clk is 2.048 MHz, "));
break;
case 0x01:
V24_PRINT (("PCM clk is 4.096 MHz, "));
break;
}
switch (G_Eeprom[CONFIG_REF_CLK])
{
case REF_CLK_8KHZ:
V24_PRINT (("REF clk is 8 kHz, "));
break;
case REF_CLK_2MHZ_1MHZEXT:
V24_PRINT (("REF clk is 2 MHz (or 1.5 MHz external), "));
break;
case REF_CLK_4MHZ_2MHZEXT:
V24_PRINT (("REF clk is 4 MHz (or 2 MHz external), "));
break;
case REF_CLK_CIF_4MHZEXT:
V24_PRINT (("REF clk is according CIF PCM, "));
break;
}
switch (G_Eeprom[CONFIG_UC_MODE] & 0x0F)
{
case 0x00:
V24_PRINT (("礐 slave, "));
break;
case 0x01:
V24_PRINT (("礐 slave, "));
break;
case 0x02:
V24_PRINT (("礐 slave, "));
break;
}
switch (G_Eeprom[CONFIG_FRAME])
{
case 0x00:
V24_PRINT (("SDSL framed, "));
break;
case 0x01:
V24_PRINT (("SDSL plesiochronous framed, "));
break;
case 0x02:
V24_PRINT (("MDSL framed, "));
break;
case 0x03:
V24_PRINT (("transparent, "));
break;
}
if (((G_Eeprom[CONFIG_UC_MODE] & 0xF0)!= 0x00) && ((G_Eeprom[CONFIG_UC_MODE] & 0xF0)!= 0xF0))
{
V24_PRINT (("\nOnly "));
if ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40)
V24_PRINT (("FALC "));
if ((G_Eeprom[CONFIG_UC_MODE] & 0x80) == 0x80)
V24_PRINT (("EPIC "));
if ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20)
V24_PRINT (("SOCRATES "));
if ((G_Eeprom[CONFIG_UC_MODE] & 0x10) == 0x10)
V24_PRINT (("BOARD "));
V24_PRINT (("initialized, "));
}
}
/* V24 control message:
When error. */
else
{
V24_PRINT (("%s ", Error_Text_Start));
V24_PRINT (("%s ", error_text));
V24_PRINT (("%s", Error_Text_End));
}
return error;
}
/* ============================= */
/* Local function definition */
/* ============================= */
/*******************************************************************************
Description:
Set board registers depending on configuration settings.
Arguments:
NONE.
Return:
BOOL - In case of wrong configuration,
function returns value FALSE, otherwise TRUE.
Remarks:
This function is called while all other devices are in reset state.
******************************************************************************/
static BOOL Set_Board_Config_Register ( void )
{
BOOL setting = TRUE;
F_TST_SET;
switch ( G_Eeprom[CONFIG_INTF] )
{
case INTF_E1_PCM_SYN:
case INTF_T1_PCM_SYN:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_EXT:
/* external timed */
REG_OE0 = 0x13; /*0x0300 */
REG_OE1 = 0x3C; /*0x0400 */
REG_MUX_SOC = 0x00; /*0x0500 */
REG_MUX_CLK = 0xA2; /*0x0600 */
switch (G_Eeprom [CONFIG_REF_CLK])
{
case REF_CLK_8KHZ:
REG_DIV0 = 0xFF; /* divider */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
REG_DIV1 = 0x01; /* divider for 4 MHz */
}
else
{
REG_DIV1 = 0x00; /* divider for 2 MHz */
}
break;
case REF_CLK_4MHZ_2MHZEXT:
/* supply 2 MHz at REFCLK also at 4 MHz */
/* data rate */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
REG_DIV0 = 0x01;
}
else
{
REG_DIV0 = 0x00;
}
REG_DIV1 = 0x00; /* divider for REF_CLK = PCLK */
break;
case REF_CLK_CIF_4MHZEXT:
/* board does not supply 2 MHz at PCLK with 4 MHz REFCLK*/
/* data rate */
REG_DIV0 = 0x00;
REG_DIV1 = 0x00; /* divider PCLK = 2 MHz */
break;
default:
// not valid
setting = FALSE;
break;
}
break;
case MODE_COT_INT:
case MODE_RT_LOOP:
/* loop / internal timed */
/* PCM interface is configured as slave */
REG_OE0 = 0x00; /*0x0300 */
REG_OE1 = 0x3F; /*0x0400 */
REG_MUX_SOC = 0x20; /*0x0500 */
REG_MUX_CLK = 0x00; /*0x0600 */
break;
case MODE_RT_FALC:
/* PCM External PLL Mode */
REG_OE0 = 0x03;
REG_OE1 = 0x3F;
REG_MUX_SOC = 0x20;
REG_MUX_CLK = 0x1A;
break;
case MODE_EXT_PLL:
/* PCM External PLL Mode */
REG_OE0 = 0x03;
REG_OE1 = 0x3F;
REG_MUX_SOC = 0x20;
REG_MUX_CLK = 0x1A;
break;
default:
setting = FALSE;
break;
}
break;
case INTF_E1_PCM_PLE:
case INTF_T1_PCM_PLE:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_INT:
case MODE_RT_LOOP:
/* PCM Plesiochronous Mode */
REG_OE0 = 0x03;
REG_OE1 = 0x3C;
REG_MUX_SOC = 0x23;
REG_MUX_CLK = 0x99;
break;
default:
setting = FALSE;
break;
}
break;
case INTF_BIT_SERIAL_0:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_EXT:
/* Bit Serial Mode, Clock Slave
RCLK and RFSC input */
/* BNC_PCLK is source for PCLK, RCLK, BNC_RCLK. This signal will be
divided and used as source for TFSC, RFSC, REF_CLK and BNC REF_CLKs */
REG_OE0 = 0x1F;
REG_OE1 = 0x18;
REG_MUX_SOC = 0x88;
REG_MUX_CLK = 0x40;
REG_DIV0 = 0x1F;
REG_DIV1 = 0x00; /* divider for standard data rate */
break;
case MODE_COT_INT:
case MODE_RT_LOOP:
/* Bit Serial Mode, Clock Master
RCLK and RFSC input */
/* TFSC is source for RFSC
PCLK is source for BNC_PCLK, RCLK and BNC_RCLK
REF_CLK is source for BNC_REF_CLK */
REG_OE0 = 0x0C;
REG_OE1 = 0x1C;
REG_MUX_SOC = 0x00;
REG_MUX_CLK = 0x00;
break;
default:
setting = FALSE;
break;
}
break;
case INTF_BIT_SERIAL_1:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_EXT:
/* Bit Serial Mode, Clock Slave
RCLK and RFSC output */
/* RFSC is source for TFSC, REF_CLK and BNC REF_CLK
RCLK is source for PCLK, BNC_RCLK and BNC_PCLK */
REG_OE0 = 0x13;
REG_OE1 = 0x1C;
REG_MUX_SOC = 0x28;
REG_MUX_CLK = 0x41;
REG_DIV0 = 0x1F;
REG_DIV1 = 0x00; /* divider for standard data rate */
break;
case MODE_COT_INT:
case MODE_RT_LOOP:
if (G_Eeprom [CONFIG_FRAME] == 1)
{
REG_OE0 = 0x02;
REG_OE1 = 0x18;
REG_MUX_SOC = 0x08;
REG_MUX_CLK = 0x40;
//pclk 2.048MHz assumed
REG_DIV0 = ((32*8) -1) % 0x100;
REG_DIV1 = ((32*8) -1) / 0x100;
}
else
{
/* Bit Serial Mode, Clock Master
RCLK and RFSC output */
/* TFSC and RFSC are source
PCLK is source for BNC_PCLK
RCLK is source for BNC_RCLK
REF_CLK is source for BNC_REF_CLK */
REG_OE0 = 0x00;
REG_OE1 = 0x1C;
REG_MUX_SOC = 0x00;
REG_MUX_CLK = 0x00;
}
break;
default:
setting = FALSE;
break;
}
break;
case INTF_T1:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_EXT:
/* PCM Plesiochronous Mode, T1 Slave */
REG_OE0 = 0x1F;
REG_OE1 = 0x3C;
REG_MUX_SOC = 0x00;
REG_MUX_CLK = 0xAA;
if (G_Eeprom [CONFIG_REF_CLK]==REF_CLK_8KHZ)
{
REG_DIV0 = 0xC0; /* divider */
REG_DIV1 = 0x00; /* divider for REF_CLK = 8 kHz */
}
/* in this mode REFCLK = SCLKR */
else
{
REG_DIV0 = 0x00;
REG_DIV1 = 0x00;
}
break;
case MODE_COT_INT:
case MODE_RT_LOOP:
/* PCM Plesiochronous Mode, T1 Master */
REG_OE0 = 0x0C;
REG_OE1 = 0x3F;
REG_MUX_SOC = 0x08;
REG_MUX_CLK = 0x08;
REG_DIV0 = 0xC0;
REG_DIV1 = 0x00;
break;
default:
setting = FALSE;
break;
}
break;
case INTF_E1_PCM_PLE_TEST:
switch ( G_Eeprom[CONFIG_MODE] )
{
case MODE_COT_EXT:
/* external timed */
REG_OE0 = 0x13; /*0x0300 */
REG_OE1 = 0x3C; /*0x0400 */
REG_MUX_SOC = 0x00; /*0x0500 */
REG_MUX_CLK = 0xA2; /*0x0600 */
switch (G_Eeprom [CONFIG_REF_CLK])
{
case REF_CLK_8KHZ:
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