📄 config.c
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/*******************************************************************************
Copyright (c) 2000, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
*******************************************************************************
Module: CONFIG
Product ID: 22622.1.0.1
Description: Contains general configuration proceedings.
******************************************************************************/
// Group= CONFIG
/* ============================= */
/* Includes */
/* ============================= */
#include <stdio.h>
#include <absacc.h>
#include "sysdef.h"
#include "dds.h"
#include "sysvar.h"
#include "sysfunc.h"
#include "reg165.h"
#include "modid.h"
/* ============================= */
/* Local Macros & Definitions */
/* ============================= */
/* Reset pulse for 1祍 */
#define RESET_TIME 40000
/* Message ID's */
#define MSG_ID_SOCRATES_CONFIG_WRITE 0
#define MSG_ID_SOCRATES_CONFIG_RECEIVED 1
#define MSG_ID_SOCRATES_CONFIG_REQ 2
#define MSG_ID_SOCRATES_CONFIG_RESET 3
#define MSG_ID_SOCRATES_BINARY_INFO 4
#define MSG_ID_SOCRATES_BINARY_INFO 4
/* Error message */
static const WORD8 Error_Text_Start[] = "Invalid";
/* Error message */
static const WORD8 Error_Text_End[] = "parameter specified";
/* ============================= */
/* Global variable definition */
/* ============================= */
WORD8 G_Eeprom [LAST_EEPROM_INDEX];
/* ============================= */
/* Local function declaration */
/* ============================= */
static BOOL Set_Board_Config_Register (void);
static void Soc_Config_Write (P_DDS_MSG pMsg);
static void Soc_Config_Req (P_DDS_MSG pMsg);
static void Soc_Config_Reset (P_DDS_MSG pMsg);
static void Soc_Binary_Info (P_DDS_MSG pMsg);
static void Config_Msg_Entry (P_DDS_MSG pMsg);
static void Reset_Mainboard (void);
/* ============================= */
/* Global function definition */
/* ============================= */
/*******************************************************************************
Description:
Inititialization function of the config module.
Arguments:
NONE.
Return:
NONE.
Remarks:
This function is calling the message entry function of this module.
******************************************************************************/
void Config_Module_Init (void)
{
printf ("\nModule CONFIG.C\t: Initialization done");
DdsSetMsgEntry (Config_Msg_Entry, MOD_ID_CONFIG_MODULE);
}
/*******************************************************************************
Description:
Initializes all devices.
Arguments:
NONE.
Return:
NONE.
Remarks:
This function is called after program startup and if Config_Write or
Config_Reset message was received. It calls several init function for
initialization of board registers (Set_Board_Config_Register),
FALC initialization (Falc_Init), initialization of EPIC (Epic_Init) and
initialization of SOCRATES (Soc_Init).
******************************************************************************/
void Initialize_Devices (void)
{
WORD16 i;
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Bring Socrates to reset state. */
if (G_Emulation_Mode != EMUL_MODE){
S_RST_SET;
}
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Bring FALC to reset state. */
F_RST_SET;
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x80) == 0x80) )
{
/* Bring EPIC to reset state. */
E_RST_SET;
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x10) == 0x10) )
{
/* Set all board config register
bits depending on chosen
configuration values. */
if (Set_Board_Config_Register () == FALSE)
V24_PRINT (("\nInitialize_Devices: wrong configuration settings"));
}
/* Interface mode is PCM: synch */
switch(G_Eeprom[CONFIG_INTF])
{
case INTF_E1_PCM_SYN:
case INTF_T1_PCM_SYN:
case INTF_E1_PCM_PLE_TEST:
/* Release reset and make
device initialization
if system mode is COT
externally timed: */
if (G_Eeprom [ CONFIG_MODE ] == MODE_COT_EXT)
{
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Release and initialize FALC. */
for(i = 0;i < RESET_TIME; i++);
F_RST_CLEAR;
Falc_Init ();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x80) == 0x80) )
{
/* Release and initialize EPIC */
for(i = 0;i < RESET_TIME; i++);
E_RST_CLEAR;
Epic_Init ();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Release and initialize Socrates */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
}
}
/* Release reset and make
device initialization
for all other possible
system modes: */
else
{
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Release and initialize Socrates. */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
DELAY();
Out (SOCRATES_TCMD, RESTR);
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Release and initialize FALC. */
for(i = 0;i < RESET_TIME; i++);
F_RST_CLEAR;
Falc_Init ();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x80) == 0x80) )
{
/* Release and initialize EPIC. */
for(i = 0;i < RESET_TIME; i++);
E_RST_CLEAR;
Epic_Init ();
}
}
break;
case INTF_E1_PCM_PLE:
case INTF_T1_PCM_PLE:
if (G_Eeprom [ CONFIG_MODE ] == MODE_COT_EXT)
{
printf("\nCOT external timed not possible in plesiochronous Mode");
}
/* Release reset and make
device initialization
for all other possible
system modes: */
else
{
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Release and initialize Socrates. */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
DELAY();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Release and initialize FALC. */
for(i = 0;i < RESET_TIME; i++);
F_RST_CLEAR;
Falc_Init ();
}
/* EPIC is not used in this mode */
}
break;
case INTF_T1:
if (G_Eeprom [ CONFIG_MODE ] == MODE_COT_EXT)
{
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Release and initialize FALC. */
for(i = 0;i < RESET_TIME; i++);
F_RST_CLEAR;
Falc_Init ();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Release and initialize Socrates */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
}
}
/* Release reset and make
device initialization
for all other possible
system modes: */
else
{
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x20) == 0x20) )
{
/* Release and initialize Socrates. */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
}
if ( ((G_Eeprom[CONFIG_UC_MODE] & 0xF0) == 0x00) || ((G_Eeprom[CONFIG_UC_MODE] & 0x40) == 0x40) )
{
/* Release and initialize FALC. */
for(i = 0;i < RESET_TIME; i++);
F_RST_CLEAR;
Falc_Init ();
}
}
break;
/* case interface mode is
bitserial: */
case INTF_BIT_SERIAL_0:
case INTF_BIT_SERIAL_1:
/* Release and initialize Socrates. */
for(i = 0;i < RESET_TIME; i++);
S_RST_CLEAR;
DELAY();
Soc_Init ();
break;
default:
printf("\nThis mode is not supported yet");
}
}
/*******************************************************************************
Description:
Checks a configuration stored in the variable G_Eeprom.
Arguments:
NONE.
Return:
WORD8 - The error code. If the configuration is ok the function
returns 0. Otherwise an error code is returned.
Remarks:
It is called before a configuration will be set. If the
configuration makes sense the function prints out the new settings.
The calling function will set the configuration. If the error code
greater 0 is returned, the calling function can abort the action or
can set the default configuration.
******************************************************************************/
WORD8 Config_Check(void)
{
WORD8 error = 0;
const WORD8 *error_text = NULL;
/* Set error text dependent on
the received parameters. */
/* Check auto start/ emulation */
if (G_Eeprom[CONFIG_AUTO] > 0x02)
{
error = 1;
error_text = "AUTO";
}
/* Check interface mode */
if (G_Eeprom[CONFIG_INTF] > 0x07)
{
error = 2;
error_text = "INTF";
}
/* Check timing mode */
if ((G_Eeprom[CONFIG_MODE] > 0x04) ||
((G_Eeprom[CONFIG_MODE] == MODE_RT_FALC) && (G_Eeprom[CONFIG_INTF] != INTF_E1_PCM_SYN)
&& (G_Eeprom[CONFIG_INTF] != INTF_E1_PCM_PLE)) ||
((G_Eeprom[CONFIG_MODE] == MODE_EXT_PLL) && (G_Eeprom[CONFIG_INTF] != INTF_E1_PCM_SYN)
&& (G_Eeprom[CONFIG_INTF] != INTF_E1_PCM_PLE)))
{
error = 3;
error_text = "MODE";
}
/* Check PCM clock setting */
if ((G_Eeprom[CONFIG_P_CLK] > P_CLK_4MHZ) ||
/* in PCM E1 slave mode P_CLK must be 2 MHz */
((G_Eeprom[CONFIG_P_CLK] != P_CLK_2MHZ) && (G_Eeprom[CONFIG_INTF] == INTF_E1_PCM_PLE) &&
((G_Eeprom[CONFIG_MODE] == MODE_COT_INT) || (G_Eeprom[CONFIG_MODE] == MODE_RT_LOOP))
))
{
error = 4;
error_text = "P_CLK";
}
/* Check REF clock setting */
if ((G_Eeprom[CONFIG_REF_CLK] > REF_CLK_CIF_4MHZEXT) ||
/* E1 synchronous allowes not
Ref Clk 8kHz in RT-FALC PLL mode */
((G_Eeprom[CONFIG_INTF] == INTF_E1_PCM_SYN) &&
((G_Eeprom[CONFIG_REF_CLK] == REF_CLK_8KHZ) && (G_Eeprom[CONFIG_MODE] == MODE_RT_FALC))
) ||
/* in external mode REF_CLK_CIF_4MHZEXT
is not possible with P_CLK 2MHz */
((G_Eeprom[CONFIG_MODE] == MODE_COT_EXT) &&
((G_Eeprom[CONFIG_REF_CLK] == REF_CLK_CIF_4MHZEXT) && (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
)) ||
/* in T1 mode external timed REFCLK must
not be 2 or 4 MHz */
((G_Eeprom[CONFIG_INTF] == INTF_T1) && (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT) &&
((G_Eeprom[CONFIG_REF_CLK] == REF_CLK_CIF_4MHZEXT) || (G_Eeprom[CONFIG_REF_CLK] == REF_CLK_4MHZ_2MHZEXT))
)
)
{
error = 5;
error_text = "REF_CLK";
}
/* Check uC mode only for uC commands */
if ((G_Eeprom[CONFIG_UC_MODE] & 0x0F) > 0x02)
{
error = 6;
error_text = "UC_MODE";
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