📄 epic.c
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}
/*******************************************************************************
Description:
Update all current timeslot connections.
Arguments:
NONE.
Return:
NONE.
Remarks:
NONE.
******************************************************************************/
void Epic_Update_Connections (void)
{
WORD8 i, Epic_delay_mode;
/* set default settings */
Epic_delay_mode = 0;
Epic_extra_switching = 0;
/* No timeslots to be switched:
reset all connections. */
if (G_Epic_Switch_Slt_Num == 0)
{
Epic_Reset_All_Connections ();
}
else
/* Set current switching
connections: */
{
/* Epic PCM Mode 1 Upstream */
if ((Epic_Pcm_Mode == 1) && ((G_Epic_Switch_Src_Prt & 0x30) == 0x10)
&& ((G_Epic_Switch_Dst_Prt & 0x30) == 0x00))
{
Epic_delay_mode = 1;
}
/* Epic PCM Mode 1 Downstream */
if ((Epic_Pcm_Mode == 1) && ((G_Epic_Switch_Src_Prt & 0x30) == 0x00)
&& ((G_Epic_Switch_Dst_Prt & 0x30) == 0x10))
{
Epic_delay_mode = 2;
}
switch (Epic_delay_mode)
{
case 1: /* Upstream */
/* Always 1 frame delay */
for (i = 0;i < G_Epic_Switch_Slt_Num; i++)
{
/* 0 frames delay */
if ((G_Epic_Switch_Src_Slt+i < 27) && (G_Epic_Switch_Dst_Slt+i >=
((((G_Epic_Switch_Src_Slt+i)%2) + G_Epic_Switch_Src_Slt+i)*2 + 8 )))
{
/* calculate if CFI1 -> PCM0
switching needs 1 frame delay */
if ( ((G_Epic_Switch_Src_Slt+i)%2==0) &&
((G_Epic_Switch_Dst_Slt+i) >= ((G_Epic_Switch_Src_Slt+i)*2+8)) &&
((G_Epic_Switch_Dst_Slt+i) <= ((G_Epic_Switch_Src_Slt+i)*2+11)) )
{
V24_PRINT(("\nCFI slot 0x%02X is switched with 1 frame delay",
G_Epic_Switch_Src_Slt+i));
}
/* Epic Switching with odd slots
on Port 1 */
Epic_extra_switching = 1;
/* CFI0 -> CFI1
add 1 frame delay */
Epic_Set_Single_Connection (G_Epic_Switch_Src_Prt, G_Epic_Switch_Src_Slt+i,
CFI_Port1, G_Epic_Switch_Src_Slt+i);
/* CFI1 -> PCM0
add 0 or 1 frame delay */
Epic_Set_Single_Connection (CFI_Port1, G_Epic_Switch_Src_Slt+i,
G_Epic_Switch_Dst_Prt, G_Epic_Switch_Dst_Slt+i);
Epic_extra_switching = 0;
}
else
{
if (((G_Epic_Switch_Src_Slt+i) > 28 && (G_Epic_Switch_Dst_Slt+i) < 4) |
((G_Epic_Switch_Src_Slt+i) == 31 && (G_Epic_Switch_Dst_Slt+i) < 8))
{
V24_PRINT(("\nCFI slot 0x%02X is switched with 1 frame delay",
G_Epic_Switch_Src_Slt+i));
}
Epic_Set_Single_Connection (G_Epic_Switch_Src_Prt, G_Epic_Switch_Src_Slt+i,
G_Epic_Switch_Dst_Prt, G_Epic_Switch_Dst_Slt+i);
}
}
break;
case 2: /* Downstream:
Check if 2 frames delay is
necessary,
Always 1 frame delay */
for (i = 0;i < G_Epic_Switch_Slt_Num; i++)
{
if ((G_Epic_Switch_Src_Slt+i < 60) && (G_Epic_Switch_Dst_Slt+i >=
(((G_Epic_Switch_Src_Slt+i - ((G_Epic_Switch_Src_Slt+i)%4)) + 6) / 2)))
{
/* need 1 frames delay */
/* PCM0 -> CFI1 0 frame delay */
Epic_Set_Single_Connection (G_Epic_Switch_Src_Prt, G_Epic_Switch_Src_Slt+i,
CFI_Port1, G_Epic_Switch_Dst_Slt+i);
/* CFI1 -> CFI0 add 1 frame delay */
Epic_Set_Single_Connection (CFI_Port1, G_Epic_Switch_Dst_Slt+i,
G_Epic_Switch_Dst_Prt, G_Epic_Switch_Dst_Slt+i);
}
else
{
Epic_Set_Single_Connection (G_Epic_Switch_Src_Prt, G_Epic_Switch_Src_Slt+i,
G_Epic_Switch_Dst_Prt, G_Epic_Switch_Dst_Slt+i);
}
}
break;
/* No const delay switching
necessary */
default :
for (i = 0;i < G_Epic_Switch_Slt_Num; i++)
{
Epic_Set_Single_Connection (G_Epic_Switch_Src_Prt, G_Epic_Switch_Src_Slt+i,
G_Epic_Switch_Dst_Prt, G_Epic_Switch_Dst_Slt+i);
}
break;
}
}
}
/* ============================= */
/* Local function definition */
/* ============================= */
/*******************************************************************************
Description:
Connect two time slots together.
Arguments:
src_port - Specifies the source port.
src_slot - Specifies the source time slot.
dst_port - Specifies the destination port.
dst_slot - Specifies the destination time slot.
Return:
NONE.
Remarks:
NONE.
******************************************************************************/
static void Epic_Set_Single_Connection (WORD8 src_port, WORD8 src_slot, WORD8 dst_port, WORD8 dst_slot)
{
WORD8 src_port_type;
WORD8 dst_port_type;
WORD8 src_port_numb;
WORD8 dst_port_numb;
WORD8 address = 0;
/* Store port type and number
values. */
src_port_type = (src_port >> 4) & 0x03;
dst_port_type = (dst_port >> 4) & 0x03;
src_port_numb = src_port & 0x03;
dst_port_numb = dst_port & 0x03;
/* FALC uses just even timeslot numbers
in 4 MHz mode */
if (G_Eeprom [CONFIG_P_CLK] == P_CLK_4MHZ)
{
if ((src_port_type == CFI) && ((src_port_numb == 0x00) | (src_port_numb == 0x01)))
{
src_slot <<= 1;
}
if ((dst_port_type == CFI) && ((dst_port_numb == 0x00) | (dst_port_numb == 0x01)))
{
dst_slot <<= 1;
}
}
/* Only used if Epic_extra_switching = 1
Set following switch:
CFI1 odd slot -> PCM0 */
if ((src_port_type == 1) && (dst_port_type == 0) && (Epic_extra_switching == 1))
{
// V24INT_PRINT(("\nextra Switch CFI->PCM: "));
/* Set upstream connection. */
address = Epic_Encode_Time_Slot (PCM, dst_port_numb, dst_slot);
address |= 0x80;
Out (EPIC_MADR , address);
// V24INT_PRINT(("(Up:)PCM_Dst=0x%02X,",address));
address = Epic_Encode_Time_Slot (CFI, src_port_numb, (src_slot+1));
address |= 0x80;
Out (EPIC_MAAR , address);
// V24INT_PRINT(("CFI_Src=0x%02X slot 0x%02X port 0x%02X",address, (src_slot+1), src_port_numb));
Out (EPIC_MACR , 0x71);
WHILE_NOT_ABORT ( In(EPIC_STAR) > 0x7F);
if (G_Abort == TRUE) printf(": EPIC_STAR0\n");
/* Release tristate. */
Out (EPIC_MADR , 0x0F);
address = Epic_Encode_Time_Slot (PCM, dst_port_numb, dst_slot);
address |= 0x80;
Out (EPIC_MAAR , address);
// V24INT_PRINT(("(Tri:)PCM_Dst=0x%02X",address));
Out (EPIC_MACR , 0x60);
WHILE_NOT_ABORT ( In (EPIC_STAR) > 0x7F);
if (G_Abort == TRUE) printf(": EPIC_STAR1\n");
}
/* Set following switch:
CFI -> PCM */
if ((src_port_type == 1) && (dst_port_type == 0) && (Epic_extra_switching != 1))
{
// V24INT_PRINT(("\nnormal Switch CFI->PCM: "));
/* Set upstream connection. */
address = Epic_Encode_Time_Slot (PCM, dst_port_numb, dst_slot);
address |= 0x80;
Out (EPIC_MADR , address);
// V24INT_PRINT(("(Up:)PCM_Dst=0x%02X,",address));
address = Epic_Encode_Time_Slot (CFI, src_port_numb, src_slot);
address |= 0x80;
Out (EPIC_MAAR , address);
// V24INT_PRINT(("CFI_Src=0x%02X slot 0x%02X port 0x%02X",address, src_slot, src_port_numb));
Out (EPIC_MACR , 0x71);
WHILE_NOT_ABORT ( In(EPIC_STAR) > 0x7F);
if (G_Abort == TRUE) printf(": EPIC_STAR2\n");
/* Release tristate. */
Out (EPIC_MADR , 0x0F);
address = Epic_Encode_Time_Slot (PCM, dst_port_numb, dst_slot);
address |= 0x80;
Out (EPIC_MAAR , address);
// V24INT_PRINT(("(Tri:)PCM_Dst=0x%02X",address));
Out (EPIC_MACR , 0x60);
WHILE_NOT_ABORT ( In (EPIC_STAR) > 0x7F);
if (G_Abort == TRUE) printf(": EPIC_STAR3\n");
}
/* Set following switch:
PCM -> CFI */
if ((src_port_type == 0) && (dst_port_type == 1))
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